Module: Mesa Branch: main Commit: f2f87d08721d53f6b5821d378b71b186e8a7deb4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f2f87d08721d53f6b5821d378b71b186e8a7deb4
Author: Samuel Pitoiset <samuel.pitoi...@gmail.com> Date: Thu Jan 11 14:31:43 2024 +0100 radv: re-organize radv_pipeline_key Rename and regroup fields per PSO basically. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27007> --- src/amd/vulkan/nir/radv_nir_lower_abi.c | 10 +++---- src/amd/vulkan/nir/radv_nir_lower_fs_barycentric.c | 2 +- src/amd/vulkan/nir/radv_nir_lower_fs_intrinsics.c | 4 +-- .../vulkan/nir/radv_nir_lower_poly_line_smooth.c | 2 +- src/amd/vulkan/nir/radv_nir_lower_vs_inputs.c | 14 ++++----- src/amd/vulkan/radv_pipeline_graphics.c | 30 +++++++++---------- src/amd/vulkan/radv_private.h | 4 +-- src/amd/vulkan/radv_shader.c | 4 +-- src/amd/vulkan/radv_shader.h | 34 +++++++++++++--------- src/amd/vulkan/radv_shader_args.c | 4 +-- src/amd/vulkan/radv_shader_info.c | 18 ++++++------ 11 files changed, 66 insertions(+), 60 deletions(-) diff --git a/src/amd/vulkan/nir/radv_nir_lower_abi.c b/src/amd/vulkan/nir/radv_nir_lower_abi.c index 97d916c9966..95ff340e0f9 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_abi.c +++ b/src/amd/vulkan/nir/radv_nir_lower_abi.c @@ -157,8 +157,8 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state) break; case nir_intrinsic_load_patch_vertices_in: if (stage == MESA_SHADER_TESS_CTRL) { - if (s->pl_key->tcs.tess_input_vertices) { - replacement = nir_imm_int(b, s->pl_key->tcs.tess_input_vertices); + if (s->pl_key->ts.patch_control_points) { + replacement = nir_imm_int(b, s->pl_key->ts.patch_control_points); } else { replacement = GET_SGPR_FIELD_NIR(s->args->tcs_offchip_layout, TCS_OFFCHIP_LAYOUT_PATCH_CONTROL_POINTS); } @@ -351,7 +351,7 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state) if (s->pl_key->dynamic_rasterization_samples) { replacement = GET_SGPR_FIELD_NIR(s->args->ps_state, PS_STATE_NUM_SAMPLES); } else { - replacement = nir_imm_int(b, s->pl_key->ps.num_samples); + replacement = nir_imm_int(b, s->pl_key->ms.rasterization_samples); } break; case nir_intrinsic_load_provoking_vtx_in_prim_amd: { @@ -359,7 +359,7 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state) replacement = ac_nir_load_arg(b, &s->args->ac, s->args->ngg_provoking_vtx); } else { unsigned provoking_vertex = 0; - if (s->pl_key->vs.provoking_vtx_last) { + if (s->pl_key->rs.provoking_vtx_last) { if (stage == MESA_SHADER_VERTEX) { provoking_vertex = radv_get_num_vertices_per_prim(s->pl_key) - 1; } else if (stage == MESA_SHADER_GEOMETRY) { @@ -489,7 +489,7 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state) nir_def *line_rast_mode = GET_SGPR_FIELD_NIR(s->args->ps_state, PS_STATE_LINE_RAST_MODE); replacement = nir_ieq_imm(b, line_rast_mode, VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_EXT); } else { - replacement = nir_imm_bool(b, s->pl_key->ps.line_smooth_enabled); + replacement = nir_imm_bool(b, s->pl_key->rs.line_smooth_enabled); } break; case nir_intrinsic_load_initial_edgeflags_amd: diff --git a/src/amd/vulkan/nir/radv_nir_lower_fs_barycentric.c b/src/amd/vulkan/nir/radv_nir_lower_fs_barycentric.c index d97c4117591..41a86b5b856 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_fs_barycentric.c +++ b/src/amd/vulkan/nir/radv_nir_lower_fs_barycentric.c @@ -266,7 +266,7 @@ radv_nir_lower_fs_barycentric(nir_shader *shader, const struct radv_pipeline_key lower_fs_barycentric_state state = { .dynamic_rasterization_samples = key->dynamic_rasterization_samples, - .num_rasterization_samples = key->ps.num_samples, + .num_rasterization_samples = key->ms.rasterization_samples, .rast_prim = rast_prim, }; diff --git a/src/amd/vulkan/nir/radv_nir_lower_fs_intrinsics.c b/src/amd/vulkan/nir/radv_nir_lower_fs_intrinsics.c index 4300f795715..8686972deb2 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_fs_intrinsics.c +++ b/src/amd/vulkan/nir/radv_nir_lower_fs_intrinsics.c @@ -52,7 +52,7 @@ radv_nir_lower_fs_intrinsics(nir_shader *nir, const struct radv_shader_stage *fs nir_def *sample_coverage = nir_load_vector_arg_amd(&b, 1, .base = args->ac.sample_coverage.arg_index); nir_def *def = NULL; - if (info->ps.uses_sample_shading || key->ps.sample_shading_enable) { + if (info->ps.uses_sample_shading || key->ms.sample_shading_enable) { /* gl_SampleMaskIn[0] = (SampleCoverage & (PsIterMask << gl_SampleID)). */ nir_def *ps_state = nir_load_scalar_arg_amd(&b, 1, .base = args->ps_state.arg_index); nir_def *ps_iter_mask = @@ -121,7 +121,7 @@ radv_nir_lower_fs_intrinsics(nir_shader *nir, const struct radv_shader_stage *fs new_dest = nir_if_phi(&b, res1, res2); } else { - if (!key->ps.num_samples) { + if (!key->ms.rasterization_samples) { new_dest = nir_load_barycentric_pixel(&b, 32, .interp_mode = nir_intrinsic_interp_mode(intrin)); } else { nir_def *sample_pos = nir_load_sample_positions_amd(&b, 32, intrin->src[0].ssa, num_samples); diff --git a/src/amd/vulkan/nir/radv_nir_lower_poly_line_smooth.c b/src/amd/vulkan/nir/radv_nir_lower_poly_line_smooth.c index f75a9611cca..b9939e0938b 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_poly_line_smooth.c +++ b/src/amd/vulkan/nir/radv_nir_lower_poly_line_smooth.c @@ -31,7 +31,7 @@ radv_should_lower_poly_line_smooth(nir_shader *nir, const struct radv_pipeline_k { nir_function_impl *impl = nir_shader_get_entrypoint(nir); - if (!key->ps.line_smooth_enabled && !key->dynamic_line_rast_mode) + if (!key->rs.line_smooth_enabled && !key->dynamic_line_rast_mode) return false; nir_foreach_block (block, impl) { diff --git a/src/amd/vulkan/nir/radv_nir_lower_vs_inputs.c b/src/amd/vulkan/nir/radv_nir_lower_vs_inputs.c index 943a2466061..11f06e3de24 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_vs_inputs.c +++ b/src/amd/vulkan/nir/radv_nir_lower_vs_inputs.c @@ -81,7 +81,7 @@ lower_load_vs_input_from_prolog(nir_builder *b, nir_intrinsic_instr *intrin, low static nir_def * calc_vs_input_index_instance_rate(nir_builder *b, unsigned location, lower_vs_inputs_state *s) { - const uint32_t divisor = s->pl_key->vs.instance_rate_divisors[location]; + const uint32_t divisor = s->pl_key->vi.instance_rate_divisors[location]; nir_def *start_instance = nir_load_base_instance(b); if (divisor == 0) @@ -94,7 +94,7 @@ calc_vs_input_index_instance_rate(nir_builder *b, unsigned location, lower_vs_in static nir_def * calc_vs_input_index(nir_builder *b, unsigned location, lower_vs_inputs_state *s) { - if (s->pl_key->vs.instance_rate_inputs & BITFIELD_BIT(location)) + if (s->pl_key->vi.instance_rate_inputs & BITFIELD_BIT(location)) return calc_vs_input_index_instance_rate(b, location, s); return nir_iadd(b, nir_load_first_vertex(b), nir_load_vertex_id_zero_base(b)); @@ -233,10 +233,10 @@ lower_load_vs_input(nir_builder *b, nir_intrinsic_instr *intrin, lower_vs_inputs if (!dest_use_mask) return nir_undef(b, dest_num_components, bit_size); - const uint32_t attrib_binding = s->pl_key->vs.vertex_attribute_bindings[location]; - const uint32_t attrib_offset = s->pl_key->vs.vertex_attribute_offsets[location]; - const uint32_t attrib_stride = s->pl_key->vs.vertex_attribute_strides[location]; - const enum pipe_format attrib_format = s->pl_key->vs.vertex_attribute_formats[location]; + const uint32_t attrib_binding = s->pl_key->vi.vertex_attribute_bindings[location]; + const uint32_t attrib_offset = s->pl_key->vi.vertex_attribute_offsets[location]; + const uint32_t attrib_stride = s->pl_key->vi.vertex_attribute_strides[location]; + const enum pipe_format attrib_format = s->pl_key->vi.vertex_attribute_formats[location]; const struct util_format_description *f = util_format_description(attrib_format); const struct ac_vtx_format_info *vtx_info = ac_get_vtx_format_info(s->rad_info->gfx_level, s->rad_info->family, attrib_format); @@ -328,7 +328,7 @@ lower_load_vs_input(nir_builder *b, nir_intrinsic_instr *intrin, lower_vs_inputs loads[num_loads++] = nir_load_buffer_amd(b, channels, bit_size, descriptor, zero, zero, index, .base = const_off, .memory_modes = nir_var_shader_in); } else { - const unsigned align_mul = MAX2(1, s->pl_key->vs.vertex_binding_align[attrib_binding]); + const unsigned align_mul = MAX2(1, s->pl_key->vi.vertex_binding_align[attrib_binding]); const unsigned align_offset = const_off % align_mul; loads[num_loads++] = nir_load_typed_buffer_amd( diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index f208eb8e423..f385bf703de 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -1828,10 +1828,10 @@ radv_generate_graphics_pipeline_key(const struct radv_device *device, const stru uint32_t offset = state->vi->attributes[i].offset; enum pipe_format format = vk_format_to_pipe_format(state->vi->attributes[i].format); - key.vs.vertex_attribute_formats[i] = format; - key.vs.vertex_attribute_bindings[i] = binding; - key.vs.vertex_attribute_offsets[i] = offset; - key.vs.instance_rate_divisors[i] = state->vi->bindings[binding].divisor; + key.vi.vertex_attribute_formats[i] = format; + key.vi.vertex_attribute_bindings[i] = binding; + key.vi.vertex_attribute_offsets[i] = offset; + key.vi.instance_rate_divisors[i] = state->vi->bindings[binding].divisor; /* vertex_attribute_strides is only needed to workaround GFX6/7 offset>=stride checks. */ if (!(pipeline->dynamic_states & RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE) && @@ -1847,11 +1847,11 @@ radv_generate_graphics_pipeline_key(const struct radv_device *device, const stru * Make sure the vertex attribute stride is zero to avoid computing a wrong offset if * it's initialized to something else than zero. */ - key.vs.vertex_attribute_strides[i] = state->vi->bindings[binding].stride; + key.vi.vertex_attribute_strides[i] = state->vi->bindings[binding].stride; } if (state->vi->bindings[binding].input_rate) { - key.vs.instance_rate_inputs |= 1u << i; + key.vi.instance_rate_inputs |= 1u << i; } const struct ac_vtx_format_info *vtx_info = @@ -1862,27 +1862,27 @@ radv_generate_graphics_pipeline_key(const struct radv_device *device, const stru * vertex_binding_align in this case. */ if (offset % attrib_align == 0) { - key.vs.vertex_binding_align[binding] = MAX2(key.vs.vertex_binding_align[binding], attrib_align); + key.vi.vertex_binding_align[binding] = MAX2(key.vi.vertex_binding_align[binding], attrib_align); } } } if (state->ts) - key.tcs.tess_input_vertices = state->ts->patch_control_points; + key.ts.patch_control_points = state->ts->patch_control_points; if (state->ms) { - key.ps.sample_shading_enable = state->ms->sample_shading_enable; + key.ms.sample_shading_enable = state->ms->sample_shading_enable; if (!(pipeline->dynamic_states & RADV_DYNAMIC_RASTERIZATION_SAMPLES) && state->ms->rasterization_samples > 1) { - key.ps.num_samples = state->ms->rasterization_samples; + key.ms.rasterization_samples = state->ms->rasterization_samples; } } if (device->physical_device->rad_info.gfx_level >= GFX11 && state->ms) { - key.ps.alpha_to_coverage_via_mrtz = state->ms->alpha_to_coverage_enable; + key.ms.alpha_to_coverage_via_mrtz = state->ms->alpha_to_coverage_enable; } if (state->ia) { - key.vs.topology = radv_translate_prim(state->ia->primitive_topology); + key.ia.topology = radv_translate_prim(state->ia->primitive_topology); } if (pipeline->base.type == RADV_PIPELINE_GRAPHICS_LIB && @@ -1892,7 +1892,7 @@ radv_generate_graphics_pipeline_key(const struct radv_device *device, const stru } if (device->physical_device->rad_info.gfx_level >= GFX10 && state->rs) { - key.vs.provoking_vtx_last = state->rs->provoking_vertex == VK_PROVOKING_VERTEX_MODE_LAST_VERTEX_EXT; + key.rs.provoking_vtx_last = state->rs->provoking_vertex == VK_PROVOKING_VERTEX_MODE_LAST_VERTEX_EXT; } key.ps.force_vrs_enabled = device->force_vrs_enabled && !radv_is_static_vrs_enabled(pipeline, state); @@ -1956,7 +1956,7 @@ radv_generate_graphics_pipeline_key(const struct radv_device *device, const stru !(lib_flags & VK_GRAPHICS_PIPELINE_LIBRARY_PRE_RASTERIZATION_SHADERS_BIT_EXT))) { key.dynamic_line_rast_mode = true; } else { - key.ps.line_smooth_enabled = + key.rs.line_smooth_enabled = state->rs && state->rs->line.mode == VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_EXT; } } @@ -2382,7 +2382,7 @@ radv_get_rasterization_prim(const struct radv_shader_stage *stages, const struct } else if (stages[MESA_SHADER_MESH].nir) { rast_prim = radv_conv_gl_prim_to_gs_out(stages[MESA_SHADER_MESH].nir->info.mesh.primitive_type); } else { - rast_prim = radv_conv_prim_to_gs_out(pipeline_key->vs.topology, false); + rast_prim = radv_conv_prim_to_gs_out(pipeline_key->ia.topology, false); } return rast_prim; diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 32fc29632e0..c3b66a2d67b 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -3174,7 +3174,7 @@ radv_primitive_topology_is_line_list(unsigned primitive_topology) static inline unsigned radv_get_num_vertices_per_prim(const struct radv_pipeline_key *pipeline_key) { - if (pipeline_key->vs.topology == V_008958_DI_PT_NONE) { + if (pipeline_key->ia.topology == V_008958_DI_PT_NONE) { /* When the topology is unknown (with graphics pipeline library), return the maximum number of * vertices per primitives for VS. This is used to lower NGG (the HW will ignore the extra * bits for points/lines) and also to enable NGG culling unconditionally (it will be disabled @@ -3183,7 +3183,7 @@ radv_get_num_vertices_per_prim(const struct radv_pipeline_key *pipeline_key) return 3; } else { /* Need to add 1, because: V_028A6C_POINTLIST=0, V_028A6C_LINESTRIP=1, V_028A6C_TRISTRIP=2, etc. */ - return radv_conv_prim_to_gs_out(pipeline_key->vs.topology, false) + 1; + return radv_conv_prim_to_gs_out(pipeline_key->ia.topology, false) + 1; } } diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 22172813bdc..492a0ee362c 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -871,7 +871,7 @@ radv_lower_ngg(struct radv_device *device, struct radv_shader_stage *ngg_stage, num_vertices_per_prim = radv_get_num_vertices_per_prim(pl_key); /* Manually mark the instance ID used, so the shader can repack it. */ - if (pl_key->vs.instance_rate_inputs) + if (pl_key->vi.instance_rate_inputs) BITSET_SET(nir->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID); } else if (nir->info.stage == MESA_SHADER_GEOMETRY) { @@ -916,7 +916,7 @@ radv_lower_ngg(struct radv_device *device, struct radv_shader_stage *ngg_stage, options.early_prim_export = info->has_ngg_early_prim_export; options.passthrough = info->is_ngg_passthrough; options.export_primitive_id = info->outinfo.export_prim_id; - options.instance_rate_inputs = pl_key->vs.instance_rate_inputs << VERT_ATTRIB_GENERIC0; + options.instance_rate_inputs = pl_key->vi.instance_rate_inputs << VERT_ATTRIB_GENERIC0; NIR_PASS_V(nir, ac_nir_lower_ngg_nogs, &options); diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 09918ac6ae0..a4be370817b 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -134,6 +134,10 @@ struct radv_pipeline_key { struct radv_shader_stage_key stage_info[MESA_VULKAN_SHADER_STAGES]; + struct { + uint8_t topology; + } ia; + struct { uint32_t instance_rate_inputs; uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS]; @@ -142,30 +146,32 @@ struct radv_pipeline_key { uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS]; uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS]; uint8_t vertex_binding_align[MAX_VBS]; - uint32_t provoking_vtx_last : 1; - uint32_t has_prolog : 1; - uint8_t topology; - } vs; + } vi; struct { - unsigned tess_input_vertices; - } tcs; + unsigned patch_control_points; + } ts; struct { - struct radv_ps_epilog_key epilog; + uint32_t provoking_vtx_last : 1; + uint32_t line_smooth_enabled : 1; + } rs; - uint8_t num_samples; + struct { bool sample_shading_enable; + bool alpha_to_coverage_via_mrtz; /* GFX11+ */ + uint8_t rasterization_samples; + } ms; - bool force_vrs_enabled; + struct vs { + bool has_prolog; + } vs; - /* Used to export alpha through MRTZ for alpha-to-coverage (GFX11+). */ - bool alpha_to_coverage_via_mrtz; + struct { + struct radv_ps_epilog_key epilog; + bool force_vrs_enabled; bool exports_mrtz_via_epilog; - bool has_epilog; - - bool line_smooth_enabled; } ps; }; diff --git a/src/amd/vulkan/radv_shader_args.c b/src/amd/vulkan/radv_shader_args.c index ed2838f8a44..c188af7f5b3 100644 --- a/src/amd/vulkan/radv_shader_args.c +++ b/src/amd/vulkan/radv_shader_args.c @@ -361,7 +361,7 @@ static bool radv_tcs_needs_state_sgpr(const struct radv_shader_info *info, const struct radv_pipeline_key *key) { /* Some values are loaded from a SGPR when dynamic states are used or when the shader is unlinked. */ - return !key->tcs.tess_input_vertices || !info->num_tess_patches || !info->inputs_linked; + return !key->ts.patch_control_points || !info->num_tess_patches || !info->inputs_linked; } static bool @@ -380,7 +380,7 @@ radv_ps_needs_state_sgpr(const struct radv_shader_info *info, const struct radv_ if (key->dynamic_line_rast_mode) return true; - if (info->ps.reads_sample_mask_in && (info->ps.uses_sample_shading || key->ps.sample_shading_enable)) + if (info->ps.reads_sample_mask_in && (info->ps.uses_sample_shading || key->ms.sample_shading_enable)) return true; /* For computing barycentrics when the primitive topology is unknown at compile time (GPL). */ diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index 7939b1af2e5..c32004aa5e1 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -387,7 +387,7 @@ gather_info_input_decl_vs(const nir_shader *nir, unsigned location, const struct const struct radv_pipeline_key *key, struct radv_shader_info *info) { if (glsl_type_is_scalar(type) || glsl_type_is_vector(type)) { - if (key->vs.instance_rate_inputs & BITFIELD_BIT(location)) { + if (key->vi.instance_rate_inputs & BITFIELD_BIT(location)) { info->vs.needs_instance_id = true; info->vs.needs_base_instance = true; } @@ -395,7 +395,7 @@ gather_info_input_decl_vs(const nir_shader *nir, unsigned location, const struct if (info->vs.use_per_attribute_vb_descs) info->vs.vb_desc_usage_mask |= BITFIELD_BIT(location); else - info->vs.vb_desc_usage_mask |= BITFIELD_BIT(key->vs.vertex_attribute_bindings[location]); + info->vs.vb_desc_usage_mask |= BITFIELD_BIT(key->vi.vertex_attribute_bindings[location]); info->vs.input_slot_usage_mask |= BITFIELD_RANGE(location, glsl_count_attribute_slots(type, false)); } else if (glsl_type_is_matrix(type) || glsl_type_is_array(type)) { @@ -445,7 +445,7 @@ gather_shader_info_vs(struct radv_device *device, const nir_shader *nir, const s * computed because using the maximum number of vertices can't work. */ info->vs.dynamic_num_verts_per_prim = - pipeline_key->vs.topology == V_008958_DI_PT_NONE && info->is_ngg && nir->xfb_info; + pipeline_key->ia.topology == V_008958_DI_PT_NONE && info->is_ngg && nir->xfb_info; if (!info->outputs_linked) info->vs.num_linked_outputs = util_last_bit64(nir->info.outputs_written); @@ -476,14 +476,14 @@ gather_shader_info_tcs(struct radv_device *device, const nir_shader *nir, const if (!(pipeline_key->dynamic_patch_control_points)) { /* Number of tessellation patches per workgroup processed by the current pipeline. */ info->num_tess_patches = - get_tcs_num_patches(pipeline_key->tcs.tess_input_vertices, nir->info.tess.tcs_vertices_out, + get_tcs_num_patches(pipeline_key->ts.patch_control_points, nir->info.tess.tcs_vertices_out, info->tcs.num_linked_inputs, info->tcs.num_linked_outputs, info->tcs.num_linked_patch_outputs, device->physical_device->hs.tess_offchip_block_dw_size, device->physical_device->rad_info.gfx_level, device->physical_device->rad_info.family); /* LDS size used by VS+TCS for storing TCS inputs and outputs. */ info->tcs.num_lds_blocks = - calculate_tess_lds_size(device->physical_device->rad_info.gfx_level, pipeline_key->tcs.tess_input_vertices, + calculate_tess_lds_size(device->physical_device->rad_info.gfx_level, pipeline_key->ts.patch_control_points, nir->info.tess.tcs_vertices_out, info->tcs.num_linked_inputs, info->num_tess_patches, info->tcs.num_linked_outputs, info->tcs.num_linked_patch_outputs); } @@ -818,7 +818,7 @@ gather_shader_info_fs(const struct radv_device *device, const nir_shader *nir, info->has_epilog && pipeline_key->ps.exports_mrtz_via_epilog && export_alpha_and_mrtz; if (!info->ps.exports_mrtz_via_epilog) { - info->ps.writes_mrt0_alpha = pipeline_key->ps.alpha_to_coverage_via_mrtz && export_alpha_and_mrtz; + info->ps.writes_mrt0_alpha = pipeline_key->ms.alpha_to_coverage_via_mrtz && export_alpha_and_mrtz; } nir_foreach_shader_in_variable (var, nir) { @@ -1629,11 +1629,11 @@ radv_link_shaders_info(struct radv_device *device, struct radv_shader_stage *pro } else { vs_stage->info.workgroup_size = ac_compute_lshs_workgroup_size( device->physical_device->rad_info.gfx_level, MESA_SHADER_VERTEX, tcs_stage->info.num_tess_patches, - pipeline_key->tcs.tess_input_vertices, tcs_stage->info.tcs.tcs_vertices_out); + pipeline_key->ts.patch_control_points, tcs_stage->info.tcs.tcs_vertices_out); tcs_stage->info.workgroup_size = ac_compute_lshs_workgroup_size( device->physical_device->rad_info.gfx_level, MESA_SHADER_TESS_CTRL, tcs_stage->info.num_tess_patches, - pipeline_key->tcs.tess_input_vertices, tcs_stage->info.tcs.tcs_vertices_out); + pipeline_key->ts.patch_control_points, tcs_stage->info.tcs.tcs_vertices_out); if (!radv_use_llvm_for_stage(device, MESA_SHADER_VERTEX)) { /* When the number of TCS input and output vertices are the same (typically 3): @@ -1647,7 +1647,7 @@ radv_link_shaders_info(struct radv_device *device, struct radv_shader_stage *pro */ vs_stage->info.vs.tcs_in_out_eq = device->physical_device->rad_info.gfx_level >= GFX9 && - pipeline_key->tcs.tess_input_vertices == tcs_stage->info.tcs.tcs_vertices_out && + pipeline_key->ts.patch_control_points == tcs_stage->info.tcs.tcs_vertices_out && vs_stage->nir->info.float_controls_execution_mode == tcs_stage->nir->info.float_controls_execution_mode; if (vs_stage->info.vs.tcs_in_out_eq)
