On Fri, Sep 3, 2010 at 10:46 AM, Marek Olšák <[email protected]> wrote: > On Fri, Sep 3, 2010 at 12:54 AM, Dave Airlie <[email protected]> wrote: >> >> > >> > - Later Radeons and NV chips: I thought that these each had their own >> > register allocators than ran after Mesa's. These should be able to do >> > the right thing. Yes? >> >> r600c doesn't have anything smart for register allocation yet. We've >> had regression reports since Eric's change >> >> https://bugs.freedesktop.org/show_bug.cgi?id=29978 > > If you mean this shader: http://fpaste.org/ejpo/ > There is nothing register allocation can do about because there are indexed > temporaries. You can reallocate temporaries starting at instruction index > 47, which is too late. Note that this shader can't run on R300->R500 because > the limit is 32 temporaries in vertex shaders. Also a lot of other > optimizations are basically unusable/inapplicable with indexed temporaries. > I'd rather have commit 5ad74779cea07cc6a19a52874cdaef8b018e2f1b reverted. I > consider this a showstopper.
I'd agree on that unless there is a nicer solution and the glsl compiler can hide it from us. Dave. _______________________________________________ mesa-dev mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-dev
