--- src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 50 +++----------------------- 1 file changed, 4 insertions(+), 46 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index 82543d4..c3050f9 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -1027,34 +1027,6 @@ fs_generator::generate_ddy(enum opcode opcode, bool negate_value) { if (opcode == FS_OPCODE_DDY_FINE) { - /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register - * Region Restrictions): - * - * In Align16 access mode, SIMD16 is not allowed for DW operations - * and SIMD8 is not allowed for DF operations. - * - * In this context, "DW operations" means "operations acting on 32-bit - * values", so it includes operations on floats. - * - * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3 - * (Instruction Compression -> Rules and Restrictions): - * - * A compressed instruction must be in Align1 access mode. Align16 - * mode instructions cannot be compressed. - * - * Similar text exists in the g45 PRM. - * - * Empirically, compressed align16 instructions using odd register - * numbers don't appear to work on Sandybridge either. - * - * On these platforms, if we're building a SIMD16 shader, we need to - * manually unroll to a pair of SIMD8 instructions. - */ - bool unroll_to_simd8 = - (dispatch_width == 16 && - (devinfo->gen == 4 || devinfo->gen == 6 || - (devinfo->gen == 7 && !devinfo->is_haswell))); - /* produce accurate derivatives */ struct brw_reg src0 = brw_reg(src.file, src.nr, 0, src.negate, src.abs, @@ -1072,24 +1044,10 @@ fs_generator::generate_ddy(enum opcode opcode, BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW); brw_push_insn_state(p); brw_set_default_access_mode(p, BRW_ALIGN_16); - if (unroll_to_simd8) { - brw_set_default_exec_size(p, BRW_EXECUTE_8); - brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); - if (negate_value) { - brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0))); - brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF); - brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0))); - } else { - brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1))); - brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF); - brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1))); - } - } else { - if (negate_value) - brw_ADD(p, dst, src1, negate(src0)); - else - brw_ADD(p, dst, src0, negate(src1)); - } + if (negate_value) + brw_ADD(p, dst, src1, negate(src0)); + else + brw_ADD(p, dst, src0, negate(src1)); brw_pop_insn_state(p); } else { /* replicate the derivative at the top-left pixel to other pixels */ -- 2.7.3 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev