This will come in handy when we implement a simd lowering pass in a
follow-up patch.
---
 src/mesa/drivers/dri/i965/brw_ir_vec4.h | 41 +++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h 
b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
index 7451f44..e271fe1 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
@@ -69,6 +69,40 @@ offset(src_reg reg, unsigned delta)
    return reg;
 }
 
+static inline void
+add_horiz_offset(backend_reg *reg, unsigned delta)
+{
+   switch (reg->file) {
+   case BAD_FILE:
+      break;
+   case MRF:
+   case VGRF:
+   case ATTR:
+   case UNIFORM: {
+      reg->offset += delta * type_sz(reg->type);
+      assert(reg->offset % 16 == 0);
+      break;
+   }
+   case ARF:
+   case FIXED_GRF: {
+      const unsigned suboffset = reg->subnr + delta * type_sz(reg->type);
+      reg->nr += suboffset / REG_SIZE;
+      reg->subnr = suboffset % REG_SIZE;
+      assert(reg->subnr % 16 == 0);
+      break;
+   }
+   default:
+      assert(delta == 0);
+   }
+}
+
+static inline src_reg
+horiz_offset(src_reg reg, unsigned delta)
+{
+   add_horiz_offset(&reg, delta);
+   return reg;
+}
+
 /**
  * Reswizzle a given source register.
  * \sa brw_swizzle().
@@ -139,6 +173,13 @@ offset(dst_reg reg, unsigned delta)
 }
 
 static inline dst_reg
+horiz_offset(dst_reg reg, unsigned delta)
+{
+   add_horiz_offset(&reg, delta);
+   return reg;
+}
+
+static inline dst_reg
 writemask(dst_reg reg, unsigned mask)
 {
    assert(reg.file != IMM);
-- 
2.7.4

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