Spilling of 64-bit data requires data shuffling for the corresponding
scratch read/write messages. This produces unsupported swizzle regions
and writemasks that we need to scalarize.
---
 src/mesa/drivers/dri/i965/brw_vec4.cpp | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index edb8a84..29ac2d6 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -2632,6 +2632,12 @@ vec4_visitor::run()
       return false;
 
    OPT(translate_64bit_mad_to_mul_add);
+
+   /* Run this before payload setup because tesselation shaders
+    * rely on it to prevent cross dvec2 regioning on DF attributes
+    * that are setup so that XY are on the second half of register and
+    * ZW are in the first half of the next.
+    */
    OPT(scalarize_df);
 
    setup_payload();
@@ -2647,6 +2653,12 @@ vec4_visitor::run()
             continue;
          spill_reg(i);
       }
+
+      /* We want to run this after spilling because 64-bit (un)spills need to
+       * emit code to shuffle 64-bit data for the 32-bit scratch read/write
+       * messages that can produce unsupported 64-bit swizzle regions.
+       */
+      OPT(scalarize_df);
    }
 
    bool allocated_without_spills = reg_allocate();
@@ -2662,6 +2674,12 @@ vec4_visitor::run()
          if (failed)
             return false;
       }
+
+      /* We want to run this after spilling because 64-bit (un)spills need to
+       * emit code to shuffle 64-bit data for the 32-bit scratch read/write
+       * messages that can produce unsupported 64-bit swizzle regions.
+       */
+      OPT(scalarize_df);
    }
 
    opt_schedule_instructions();
-- 
2.7.4

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