From: Marek Olšák <marek.ol...@amd.com>
these names were misleading.
---
src/gallium/drivers/radeon/r600_test_dma.c | 2 +-
src/gallium/drivers/radeon/r600_texture.c | 10 +++++-----
src/gallium/drivers/radeon/radeon_video.c | 4 ++--
src/gallium/drivers/radeon/radeon_winsys.h | 4 ++--
src/gallium/drivers/radeonsi/cik_sdma.c | 2 +-
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 10 +++++-----
src/gallium/winsys/radeon/drm/radeon_drm_surface.c | 8 ++++----
7 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_test_dma.c
b/src/gallium/drivers/radeon/r600_test_dma.c
index 1e60f6a..7f4a8c0 100644
--- a/src/gallium/drivers/radeon/r600_test_dma.c
+++ b/src/gallium/drivers/radeon/r600_test_dma.c
@@ -294,21 +294,21 @@ void r600_test_dma(struct r600_common_screen *rscreen)
i, tdst.width0, tdst.height0, tdst.array_size,
array_mode_to_string(rdst->surface.level[0].mode),
tsrc.width0, tsrc.height0, tsrc.array_size,
array_mode_to_string(rsrc->surface.level[0].mode), bpp);
fflush(stdout);
/* set src pixels */
set_random_pixels(ctx, src, &src_cpu);
/* clear dst pixels */
- rctx->clear_buffer(ctx, dst, 0, rdst->surface.bo_size, 0, true);
+ rctx->clear_buffer(ctx, dst, 0, rdst->surface.surf_size, 0,
true);
memset(dst_cpu.ptr, 0, dst_cpu.layer_stride * tdst.array_size);
/* preparation */
max_width = MIN2(tsrc.width0, tdst.width0);
max_height = MIN2(tsrc.height0, tdst.height0);
max_depth = MIN2(tsrc.array_size, tdst.array_size);
num = do_partial_copies ? num_partial_copies : 1;
for (j = 0; j < num; j++) {
int width, height, depth;
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index dcfa7cd..ca82a74 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -630,22 +630,22 @@ void r600_texture_get_fmask_info(struct
r600_common_screen *rscreen,
assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) /
64;
if (out->slice_tile_max)
out->slice_tile_max -= 1;
out->tile_mode_index = fmask.tiling_index[0];
out->pitch_in_pixels = fmask.level[0].nblk_x;
out->bank_height = fmask.bankh;
- out->alignment = MAX2(256, fmask.bo_alignment);
- out->size = fmask.bo_size;
+ out->alignment = MAX2(256, fmask.surf_alignment);
+ out->size = fmask.surf_size;
}
static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
struct r600_texture *rtex)
{
r600_texture_get_fmask_info(rscreen, rtex,
rtex->resource.b.b.nr_samples,
&rtex->fmask);
rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment);
rtex->size = rtex->fmask.offset + rtex->fmask.size;
@@ -909,21 +909,21 @@ void r600_print_texture_info(struct r600_texture *rtex,
FILE *f)
"bpe=%u, nsamples=%u, flags=0x%x, %s\n",
rtex->resource.b.b.width0, rtex->resource.b.b.height0,
rtex->resource.b.b.depth0, rtex->surface.blk_w,
rtex->surface.blk_h,
rtex->resource.b.b.array_size, rtex->resource.b.b.last_level,
rtex->surface.bpe, rtex->resource.b.b.nr_samples,
rtex->surface.flags,
util_format_short_name(rtex->resource.b.b.format));
fprintf(f, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, "
"bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u,
scanout=%u\n",
- rtex->surface.bo_size, rtex->surface.bo_alignment,
rtex->surface.bankw,
+ rtex->surface.surf_size, rtex->surface.surf_alignment,
rtex->surface.bankw,
rtex->surface.bankh, rtex->surface.num_banks,
rtex->surface.mtilea,
rtex->surface.tile_split, rtex->surface.pipe_config,
(rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
if (rtex->fmask.size)
fprintf(f, " FMask: offset=%"PRIu64", size=%"PRIu64",
alignment=%u, pitch_in_pixels=%u, "
"bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
rtex->fmask.offset, rtex->fmask.size,
rtex->fmask.alignment,
rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
rtex->fmask.slice_tile_max,
rtex->fmask.tile_mode_index);
@@ -1007,21 +1007,21 @@ r600_texture_create_object(struct pipe_screen *screen,
resource->b.b = *base;
resource->b.b.next = NULL;
resource->b.vtbl = &r600_texture_vtbl;
pipe_reference_init(&resource->b.b.reference, 1);
resource->b.b.screen = screen;
/* don't include stencil-only formats which we don't support for
rendering */
rtex->is_depth =
util_format_has_depth(util_format_description(rtex->resource.b.b.format));
rtex->surface = *surface;
- rtex->size = rtex->surface.bo_size;
+ rtex->size = rtex->surface.surf_size;
rtex->tc_compatible_htile = rtex->surface.htile_size != 0;
assert(!!(rtex->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE) ==
rtex->tc_compatible_htile);
/* TC-compatible HTILE only supports Z32_FLOAT. */
if (rtex->tc_compatible_htile)
rtex->db_render_format = PIPE_FORMAT_Z32_FLOAT;
else
rtex->db_render_format = base->format;
@@ -1081,21 +1081,21 @@ r600_texture_create_object(struct pipe_screen *screen,
!(rtex->surface.flags & RADEON_SURF_SCANOUT)) {
/* Reserve space for the DCC buffer. */
rtex->dcc_offset = align64(rtex->size,
rtex->surface.dcc_alignment);
rtex->size = rtex->dcc_offset + rtex->surface.dcc_size;
}
}
/* Now create the backing buffer. */
if (!buf) {
r600_init_resource_fields(rscreen, resource, rtex->size,
- rtex->surface.bo_alignment);
+ rtex->surface.surf_alignment);
resource->flags |= RADEON_FLAG_HANDLE;
if (!r600_alloc_resource(rscreen, resource)) {
FREE(rtex);
return NULL;
}
} else {
resource->buf = buf;
resource->gpu_address =
rscreen->ws->buffer_get_virtual_address(resource->buf);
diff --git a/src/gallium/drivers/radeon/radeon_video.c
b/src/gallium/drivers/radeon/radeon_video.c
index de8e11c..b4fd306 100644
--- a/src/gallium/drivers/radeon/radeon_video.c
+++ b/src/gallium/drivers/radeon/radeon_video.c
@@ -165,24 +165,24 @@ void rvid_join_surfaces(struct radeon_winsys* ws,
if (!surfaces[i])
continue;
/* copy the tiling parameters */
surfaces[i]->bankw = surfaces[best_tiling]->bankw;
surfaces[i]->bankh = surfaces[best_tiling]->bankh;
surfaces[i]->mtilea = surfaces[best_tiling]->mtilea;
surfaces[i]->tile_split = surfaces[best_tiling]->tile_split;
/* adjust the texture layer offsets */
- off = align(off, surfaces[i]->bo_alignment);
+ off = align(off, surfaces[i]->surf_alignment);
for (j = 0; j < ARRAY_SIZE(surfaces[i]->level); ++j)
surfaces[i]->level[j].offset += off;
- off += surfaces[i]->bo_size;
+ off += surfaces[i]->surf_size;
}
for (i = 0, size = 0, alignment = 0; i < VL_NUM_COMPONENTS; ++i) {
if (!buffers[i] || !*buffers[i])
continue;
size = align(size, (*buffers[i])->alignment);
size += (*buffers[i])->size;
alignment = MAX2(alignment, (*buffers[i])->alignment * 1);
}
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index 29b64c0..cec1274 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -290,22 +290,22 @@ struct radeon_surf {
/* Format properties. */
unsigned blk_w:4;
unsigned blk_h:4;
unsigned bpe:5;
uint32_t flags;
/* These are return values. Some of them can be set by the caller, but
* they will be treated as hints (e.g. bankw, bankh) and might be
* changed by the calculator.
*/
- uint64_t bo_size;
- uint32_t bo_alignment;
+ uint64_t surf_size;
+ uint32_t surf_alignment;
/* This applies to EG and later. */
unsigned bankw:4; /* max 8 */
unsigned bankh:4; /* max 8 */
unsigned mtilea:4; /* max 8 */
unsigned tile_split:13; /* max 4K */
unsigned stencil_tile_split:13; /* max 4K */
unsigned pipe_config:5; /* max 17 */
unsigned num_banks:5; /* max 16 */
unsigned macro_tile_index:4; /* max 15 */
diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c
b/src/gallium/drivers/radeonsi/cik_sdma.c
index 3a18118..338c0cf 100644
--- a/src/gallium/drivers/radeonsi/cik_sdma.c
+++ b/src/gallium/drivers/radeonsi/cik_sdma.c
@@ -335,21 +335,21 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
linear->surface.level[linear_level].offset +
bpp * ((linear_z + copy_depth - 1) * linear_slice_pitch
+
(linear_y + copy_height - 1) * linear_pitch +
(linear_x + copy_width));
if ((tiled_x + copy_width) % granularity)
end_linear_address += granularity -
(tiled_x + copy_width) %
granularity;
if (start_linear_address < 0 ||
- end_linear_address > linear->surface.bo_size)
+ end_linear_address > linear->surface.surf_size)
return false;
/* Check requirements. */
if (tiled_address % 256 == 0 &&
linear_address % 4 == 0 &&
linear_pitch % xalign == 0 &&
linear_x % xalign == 0 &&
tiled_x % xalign == 0 &&
copy_width_aligned % xalign == 0 &&
tiled_micro_mode != V_009910_ADDR_SURF_ROTATED_MICRO_TILING
&&
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index e6a2618..27c425c 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -182,21 +182,21 @@ static int compute_level(struct amdgpu_winsys *ws,
}
ret = AddrComputeSurfaceInfo(ws->addrlib,
AddrSurfInfoIn,
AddrSurfInfoOut);
if (ret != ADDR_OK) {
return ret;
}
surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level];
- surf_level->offset = align64(surf->bo_size, AddrSurfInfoOut->baseAlign);
+ surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
surf_level->slice_size = AddrSurfInfoOut->sliceSize;
surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 :
surf->bpe);
surf_level->nblk_x = AddrSurfInfoOut->pitch;
surf_level->nblk_y = AddrSurfInfoOut->height;
switch (AddrSurfInfoOut->tileMode) {
case ADDR_TM_LINEAR_ALIGNED:
surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
break;
case ADDR_TM_1D_TILED_THIN1:
@@ -207,21 +207,21 @@ static int compute_level(struct amdgpu_winsys *ws,
break;
default:
assert(0);
}
if (is_stencil)
surf->stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
else
surf->tiling_index[level] = AddrSurfInfoOut->tileIndex;
- surf->bo_size = surf_level->offset + AddrSurfInfoOut->surfSize;
+ surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
/* Clear DCC fields at the beginning. */
surf_level->dcc_offset = 0;
surf_level->dcc_enabled = false;
/* The previous level's flag tells us if we can use DCC for this level. */
if (AddrSurfInfoIn->flags.dccCompatible &&
(level == 0 || AddrDccOut->subLvlCompressible)) {
AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
@@ -477,36 +477,36 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
else
AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
/* Addrlib doesn't set this if tileIndex is forced like above. */
AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
}
}
- surf->bo_size = 0;
+ surf->surf_size = 0;
surf->dcc_size = 0;
surf->dcc_alignment = 1;
surf->htile_size = 0;
surf->htile_alignment = 1;
/* Calculate texture layout information. */
for (level = 0; level <= tex->last_level; level++) {
r = compute_level(ws, tex, surf, false, level, compressed,
&AddrSurfInfoIn, &AddrSurfInfoOut,
&AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
if (r)
return r;
if (level == 0) {
- surf->bo_alignment = AddrSurfInfoOut.baseAlign;
+ surf->surf_alignment = AddrSurfInfoOut.baseAlign;
surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
set_micro_tile_mode(surf, &ws->info);
/* For 2D modes only. */
if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
surf->bankw = AddrSurfInfoOut.pTileInfo->bankWidth;
surf->bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
surf->mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
surf->tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
surf->num_banks = AddrSurfInfoOut.pTileInfo->banks;
@@ -545,21 +545,21 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
}
}
}
}
/* Recalculate the whole DCC miptree size including disabled levels.
* This is what addrlib does, but calling addrlib would be a lot more
* complicated.
*/
if (surf->dcc_size && tex->last_level > 0) {
- surf->dcc_size = align64(surf->bo_size >> 8,
+ surf->dcc_size = align64(surf->surf_size >> 8,
ws->info.pipe_interleave_bytes *
ws->info.num_tile_pipes);
}
/* Make sure HTILE covers the whole miptree, because the shader reads
* TC-compatible HTILE even for levels where it's disabled by DB.
*/
if (surf->htile_size && tex->last_level)
surf->htile_size *= 2;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
index e35f8a4..fed96ee 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
@@ -139,22 +139,22 @@ static void surf_winsys_to_drm(struct radeon_surface
*surf_drm,
surf_drm->array_size = tex->array_size;
break;
case PIPE_TEXTURE_CUBE:
surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
break;
case PIPE_BUFFER:
default:
assert(0);
}
- surf_drm->bo_size = surf_ws->bo_size;
- surf_drm->bo_alignment = surf_ws->bo_alignment;
+ surf_drm->bo_size = surf_ws->surf_size;
+ surf_drm->bo_alignment = surf_ws->surf_alignment;
surf_drm->bankw = surf_ws->bankw;
surf_drm->bankh = surf_ws->bankh;
surf_drm->mtilea = surf_ws->mtilea;
surf_drm->tile_split = surf_ws->tile_split;
surf_drm->stencil_tile_split = surf_ws->stencil_tile_split;
for (i = 0; i < RADEON_SURF_MAX_LEVELS; i++) {
surf_level_winsys_to_drm(&surf_drm->level[i], &surf_ws->level[i]);
surf_level_winsys_to_drm(&surf_drm->stencil_level[i],
@@ -171,22 +171,22 @@ static void surf_drm_to_winsys(struct radeon_drm_winsys
*ws,
{
int i;
memset(surf_ws, 0, sizeof(*surf_ws));
surf_ws->blk_w = surf_drm->blk_w;
surf_ws->blk_h = surf_drm->blk_h;
surf_ws->bpe = surf_drm->bpe;
surf_ws->flags = surf_drm->flags;
- surf_ws->bo_size = surf_drm->bo_size;
- surf_ws->bo_alignment = surf_drm->bo_alignment;
+ surf_ws->surf_size = surf_drm->bo_size;
+ surf_ws->surf_alignment = surf_drm->bo_alignment;
surf_ws->bankw = surf_drm->bankw;
surf_ws->bankh = surf_drm->bankh;
surf_ws->mtilea = surf_drm->mtilea;
surf_ws->tile_split = surf_drm->tile_split;
surf_ws->stencil_tile_split = surf_drm->stencil_tile_split;
surf_ws->macro_tile_index = cik_get_macro_tile_index(surf_ws);
for (i = 0; i < RADEON_SURF_MAX_LEVELS; i++) {
--
2.7.4
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