From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeon/radeon_winsys.h | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index cec1274..2330cdd 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -291,21 +291,26 @@ struct radeon_surf {
unsigned blk_w:4;
unsigned blk_h:4;
unsigned bpe:5;
uint32_t flags;
/* These are return values. Some of them can be set by the caller, but
* they will be treated as hints (e.g. bankw, bankh) and might be
* changed by the calculator.
*/
uint64_t surf_size;
+ uint64_t dcc_size;
+ uint64_t htile_size;
+
uint32_t surf_alignment;
+ uint32_t dcc_alignment;
+ uint32_t htile_alignment;
/* This applies to EG and later. */
unsigned bankw:4; /* max 8 */
unsigned bankh:4; /* max 8 */
unsigned mtilea:4; /* max 8 */
unsigned tile_split:13; /* max 4K */
unsigned stencil_tile_split:13; /* max 4K */
unsigned pipe_config:5; /* max 17 */
unsigned num_banks:5; /* max 16 */
unsigned macro_tile_index:4; /* max 15 */
@@ -316,25 +321,20 @@ struct radeon_surf {
* compatibility. If either is true, the corresponding plane cannot be
* sampled from.
*/
unsigned depth_adjusted:1;
unsigned stencil_adjusted:1;
struct radeon_surf_level level[RADEON_SURF_MAX_LEVELS];
struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVELS];
uint8_t tiling_index[RADEON_SURF_MAX_LEVELS];
uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
-
- uint64_t dcc_size;
- uint32_t dcc_alignment;
- uint64_t htile_size;
- uint32_t htile_alignment;
};
struct radeon_bo_list_item {
uint64_t bo_size;
uint64_t vm_address;
uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
};
struct radeon_winsys {
/**
--
2.7.4
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