Am 31.01.2017 16:43, schrieb Deucher, Alexander:
-----Original Message-----
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Dieter Nützel
Sent: Tuesday, January 31, 2017 6:25 AM
To: Michel Dänzer
Cc: Alex Deucher; mesa-dev@lists.freedesktop.org; amd-
g...@lists.freedesktop.org
Subject: Re: [Mesa-dev] [PATCH] drm/radeon: Fix vram_size/visible
values in
DRM_RADEON_GEM_INFO ioctl
Hello Michel,
as this is for radeon, do you think this could/should fix
the wrong reported VRAM size with Unigine_Heaven/-Valley, too?
Maybe speed things up? ;-)
Unigine_Valley-1.0
GPU: Unknown GPU x1
System memory: 24102 MB
Video memory: 256 MB
Sync threads: 7
Async threads: 8
I'll try patching openSUSE Kernel:stable 4.9.6-2 with this
and maybe this could then go into 4.10-rc7 'cause it is a
bugfix. - Alex?
This patch just fixes the case of the HUD reporting the wrong amount
of visible vram. Most 3D apps just default to 256MB if they don't
know how much vram is. The problem is GL never provided a core way to
determine how much vram is available on a GPU so lots of vendor
specific extensions and driver specific methods popped up to address
this.
Alex
Ah, no hurry then.
Thanks for clarification.
Dieter
Greetings,
Dieter
Am 31.01.2017 07:54, schrieb Michel Dänzer:
> From: Michel Dänzer <michel.daen...@amd.com>
>
> vram_size is supposed to be the total amount of VRAM that can be used
> by
> userspace, which corresponds to the TTM VRAM manager size (which is
> normally the full amount of VRAM, but can be just the visible VRAM when
> DMA can't be used for BO migration for some reason).
>
> The above was incorrectly used for vram_visible before, resulting in
> generally too large values being reported.
>
> Signed-off-by: Michel Dänzer <michel.daen...@amd.com>
> ---
> drivers/gpu/drm/radeon/radeon_drv.c | 3 ++-
> drivers/gpu/drm/radeon/radeon_gem.c | 4 ++--
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_drv.c
> b/drivers/gpu/drm/radeon/radeon_drv.c
> index a252bc407aa2..88c41d43ec3d 100644
> --- a/drivers/gpu/drm/radeon/radeon_drv.c
> +++ b/drivers/gpu/drm/radeon/radeon_drv.c
> @@ -97,9 +97,10 @@
> * 2.46.0 - Add PFP_SYNC_ME support on evergreen
> * 2.47.0 - Add UVD_NO_OP register support
> * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
> + * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct
> vram_size/visible values
> */
> #define KMS_DRIVER_MAJOR 2
> -#define KMS_DRIVER_MINOR 48
> +#define KMS_DRIVER_MINOR 49
> #define KMS_DRIVER_PATCHLEVEL 0
> int radeon_driver_load_kms(struct drm_device *dev, unsigned long
> flags);
> int radeon_driver_unload_kms(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/radeon/radeon_gem.c
> b/drivers/gpu/drm/radeon/radeon_gem.c
> index 0bcffd8a7bd3..96683f5b2b1b 100644
> --- a/drivers/gpu/drm/radeon/radeon_gem.c
> +++ b/drivers/gpu/drm/radeon/radeon_gem.c
> @@ -220,8 +220,8 @@ int radeon_gem_info_ioctl(struct drm_device *dev,
> void *data,
>
> man = &rdev->mman.bdev.man[TTM_PL_VRAM];
>
> - args->vram_size = rdev->mc.real_vram_size;
> - args->vram_visible = (u64)man->size << PAGE_SHIFT;
> + args->vram_size = (u64)man->size << PAGE_SHIFT;
> + args->vram_visible = rdev->mc.visible_vram_size;
> args->vram_visible -= rdev->vram_pin_size;
> args->gart_size = rdev->mc.gtt_size;
> args->gart_size -= rdev->gart_pin_size;
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