From: Frans Gu <frans...@amd.com>
Switch the tile index based on logic instead of hardcoded threshold
for different ASIC.
---
src/amd/addrlib/r800/ciaddrlib.cpp | 68 +++++++++++---------------------------
src/amd/addrlib/r800/ciaddrlib.h | 2 --
2 files changed, 19 insertions(+), 51 deletions(-)
diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp
b/src/amd/addrlib/r800/ciaddrlib.cpp
index 97ef3b6..64fa669 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -905,63 +905,20 @@ BOOL_32 CiAddrLib::HwlOverrideTileMode(
{
*pTileMode = tileMode;
bOverrided = TRUE;
}
return bOverrided;
}
/**
***************************************************************************************************
-* CiAddrLib::GetPrtSwitchP4Threshold
-*
-* @brief
-* Return the threshold of switching to P4_* instead of P16_* for PRT
resources
-***************************************************************************************************
-*/
-UINT_32 CiAddrLib::GetPrtSwitchP4Threshold() const
-{
- UINT_32 threshold;
-
- switch (m_pipes)
- {
- case 8:
- threshold = 32;
- break;
- case 16:
- if (m_settings.isFiji)
- {
- threshold = 16;
- }
- else if (m_settings.isHawaii)
- {
- threshold = 8;
- }
- else
- {
- ///@todo add for possible new ASICs.
- ADDR_ASSERT_ALWAYS();
- threshold = 16;
- }
- break;
- default:
- ///@todo add for possible new ASICs.
- ADDR_ASSERT_ALWAYS();
- threshold = 32;
- break;
- }
-
- return threshold;
-}
-
-/**
-***************************************************************************************************
* CiAddrLib::HwlSetupTileInfo
*
* @brief
* Setup default value of tile info for SI
***************************************************************************************************
*/
VOID CiAddrLib::HwlSetupTileInfo(
AddrTileMode tileMode, ///< [in] Tile mode
ADDR_SURFACE_FLAGS flags, ///< [in] Surface type
flags
UINT_32 bpp, ///< [in] Bits per
pixel
@@ -1178,30 +1135,43 @@ VOID CiAddrLib::HwlSetupTileInfo(
default:
break;
}
}
if (m_pipes >= 8)
{
ADDR_ASSERT((index + 1) < static_cast<INT_32>(m_noOfEntries));
// Only do this when tile mode table is updated.
if (((tileMode == ADDR_TM_PRT_TILED_THIN1) || (tileMode ==
ADDR_TM_PRT_TILED_THICK)) &&
- (m_tileTable[index+1].mode == tileMode))
+ (m_tileTable[index + 1].mode == tileMode))
{
- UINT_32 bytesXSamples = bpp * numSamples / 8;
- UINT_32 bytesXThickness = bpp * thickness / 8;
- UINT_32 switchP4Threshold = GetPrtSwitchP4Threshold();
+ static const UINT_32 PrtTileBytes = 0x10000;
+ ADDR_TILEINFO tileInfo = {0};
+
+ HwlComputeMacroModeIndex(index, flags, bpp, numSamples,
&tileInfo);
+
+ UINT_32 macroTileBytes = (bpp >> 3) * 64 * numSamples *
thickness *
+ HwlGetPipes(&tileInfo) *
tileInfo.banks *
+ tileInfo.bankWidth *
tileInfo.bankHeight;
- if ((bytesXSamples > switchP4Threshold) || (bytesXThickness >
switchP4Threshold))
+ if (macroTileBytes != PrtTileBytes)
{
- // Pick next 4 pipe entry
+ // Switching to next tile mode entry to make sure macro
tile size is 64KB
index += 1;
+
+ tileInfo.pipeConfig = m_tileTable[index].info.pipeConfig;
+
+ macroTileBytes = (bpp >> 3) * 64 * numSamples * thickness *
+ HwlGetPipes(&tileInfo) * tileInfo.banks *
+ tileInfo.bankWidth * tileInfo.bankHeight;
+
+ ADDR_ASSERT(macroTileBytes == PrtTileBytes);
}
}
}
}
else
{
// A pre-filled tile info is ready
index = pOut->tileIndex;
macroModeIndex = pOut->macroModeIndex;
diff --git a/src/amd/addrlib/r800/ciaddrlib.h b/src/amd/addrlib/r800/ciaddrlib.h
index 92d8468..92997a5 100644
--- a/src/amd/addrlib/r800/ciaddrlib.h
+++ b/src/amd/addrlib/r800/ciaddrlib.h
@@ -162,22 +162,20 @@ protected:
UINT_32* pPitch, UINT_32 pitchAlign, UINT_32* pHeight, UINT_32
heightAlign,
UINT_32* pSlices, UINT_32 sliceAlign) const;
private:
VOID ReadGbTileMode(
UINT_32 regValue, ADDR_TILECONFIG* pCfg) const;
VOID ReadGbMacroTileCfg(
UINT_32 regValue, ADDR_TILEINFO* pCfg) const;
- UINT_32 GetPrtSwitchP4Threshold() const;
-
BOOL_32 InitTileSettingTable(
const UINT_32 *pSetting, UINT_32 noOfEntries);
BOOL_32 InitMacroTileCfgTable(
const UINT_32 *pSetting, UINT_32 noOfEntries);
UINT_64 HwlComputeMetadataNibbleAddress(
UINT_64 uncompressedDataByteAddress,
UINT_64 dataBaseByteAddress,
UINT_64 metadataBaseByteAddress,
--
2.7.4
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