From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeon/r600_pipe_common.h | 6 ++++++
src/gallium/drivers/radeon/r600_texture.c | 11 +++++------
src/gallium/drivers/radeonsi/si_blit.c | 6 ++----
src/gallium/drivers/radeonsi/si_descriptors.c | 5 ++---
src/gallium/drivers/radeonsi/si_state.c | 2 +-
5 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 3516884..53fce50 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -941,20 +941,26 @@ r600_get_sampler_view_priority(struct r600_resource *res)
return RADEON_PRIO_SAMPLER_TEXTURE;
}
static inline bool
r600_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
{
return (stencil_sampler && tex->can_sample_s) ||
(!stencil_sampler && tex->can_sample_z);
}
+static inline bool
+vi_dcc_enabled(struct r600_texture *tex, unsigned level)
+{
+ return tex->dcc_offset && level < tex->surface.num_dcc_levels;
+}
+
#define COMPUTE_DBG(rscreen, fmt, args...) \
do { \
if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr,
fmt, ##args); \
} while (0);
#define R600_ERR(fmt, args...) \
fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__,
##args)
/* For MSAA sample positions. */
#define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index ec7a325..94024c8 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -65,22 +65,22 @@ bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx,
* When dst is linear, the DB->CB copy preserves HTILE.
* When dst is tiled, the 3D path must be used to update HTILE.
*/
if (rsrc->is_depth || rdst->is_depth)
return false;
/* DCC as:
* src: Use the 3D path. DCC decompression is expensive.
* dst: Use the 3D path to compress the pixels with DCC.
*/
- if ((rsrc->dcc_offset && src_level < rsrc->surface.num_dcc_levels) ||
- (rdst->dcc_offset && dst_level < rdst->surface.num_dcc_levels))
+ if (vi_dcc_enabled(rsrc, src_level) ||
+ vi_dcc_enabled(rdst, dst_level))
return false;
/* CMASK as:
* src: Both texture and SDMA paths need decompression. Use SDMA.
* dst: If overwriting the whole texture, discard CMASK and use
* SDMA. Otherwise, use the 3D path.
*/
if (rdst->cmask.size && rdst->dirty_level_mask & (1 << dst_level)) {
/* The CMASK clear is only enabled for the first level. */
assert(dst_level == 0);
@@ -1740,22 +1740,21 @@ bool vi_dcc_formats_compatible(enum pipe_format format1,
type1 == type2;
}
void vi_dcc_disable_if_incompatible_format(struct r600_common_context *rctx,
struct pipe_resource *tex,
unsigned level,
enum pipe_format view_format)
{
struct r600_texture *rtex = (struct r600_texture *)tex;
- if (rtex->dcc_offset &&
- level < rtex->surface.num_dcc_levels &&
+ if (vi_dcc_enabled(rtex, level) &&
!vi_dcc_formats_compatible(tex->format, view_format))
if (!r600_texture_disable_dcc(rctx, (struct r600_texture*)tex))
rctx->decompress_dcc(&rctx->b, rtex);
}
struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
struct pipe_resource *texture,
const struct pipe_surface
*templ,
unsigned width, unsigned height)
{
@@ -2307,21 +2306,21 @@ static bool vi_get_fast_clear_parameters(enum
pipe_format surface_format,
return true;
}
void vi_dcc_clear_level(struct r600_common_context *rctx,
struct r600_texture *rtex,
unsigned level, unsigned clear_value)
{
struct pipe_resource *dcc_buffer;
uint64_t dcc_offset;
- assert(rtex->dcc_offset && level < rtex->surface.num_dcc_levels);
+ assert(vi_dcc_enabled(rtex, level));
if (rtex->dcc_separate_buffer) {
dcc_buffer = &rtex->dcc_separate_buffer->b.b;
dcc_offset = 0;
} else {
dcc_buffer = &rtex->resource.b.b;
dcc_offset = rtex->dcc_offset;
}
dcc_offset += rtex->surface.level[level].dcc_offset;
@@ -2478,21 +2477,21 @@ void evergreen_do_fast_color_clear(struct
r600_common_context *rctx,
/* Stoney can't do a CMASK-based clear, so all clears
are
* considered to be hypothetically slow clears, which
* is weighed when determining to enable separate DCC.
*/
if (tex->dcc_gather_statistics &&
rctx->family == CHIP_STONEY)
tex->num_slow_clears++;
}
/* Try to clear DCC first, otherwise try CMASK. */
- if (tex->dcc_offset && tex->surface.num_dcc_levels) {
+ if (vi_dcc_enabled(tex, 0)) {
uint32_t reset_value;
bool clear_words_needed;
if (rctx->screen->debug_flags & DBG_NO_DCC_CLEAR)
continue;
if (!vi_get_fast_clear_parameters(fb->cbufs[i]->format,
color, &reset_value,
&clear_words_needed))
continue;
diff --git a/src/gallium/drivers/radeonsi/si_blit.c
b/src/gallium/drivers/radeonsi/si_blit.c
index da6c0cd..0466f19 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -420,22 +420,21 @@ static void si_blit_decompress_color(struct pipe_context
*ctx,
if (!need_dcc_decompress)
level_mask &= rtex->dirty_level_mask;
if (!level_mask)
return;
if (rtex->dcc_offset && need_dcc_decompress) {
custom_blend = sctx->custom_blend_dcc_decompress;
/* disable levels without DCC */
for (int i = first_level; i <= last_level; i++) {
- if (!rtex->dcc_offset ||
- i >= rtex->surface.num_dcc_levels)
+ if (!vi_dcc_enabled(rtex, i))
level_mask &= ~(1 << i);
}
} else if (rtex->fmask.size) {
custom_blend = sctx->custom_blend_decompress;
} else {
custom_blend = sctx->custom_blend_fastclear;
}
while (level_mask) {
unsigned level = u_bit_scan(&level_mask);
@@ -1026,22 +1025,21 @@ static bool do_hardware_msaa_resolve(struct
pipe_context *ctx,
*/
src->last_msaa_resolve_target_micro_mode =
dst->surface.micro_tile_mode;
goto resolve_to_temp;
}
/* Resolving into a surface with DCC is unsupported. Since
* it's being overwritten anyway, clear it to uncompressed.
* This is still the fastest codepath even with this clear.
*/
- if (dst->dcc_offset &&
- info->dst.level < dst->surface.num_dcc_levels) {
+ if (vi_dcc_enabled(dst, info->dst.level)) {
vi_dcc_clear_level(&sctx->b, dst, info->dst.level,
0xFFFFFFFF);
dst->dirty_level_mask &= ~(1 << info->dst.level);
}
/* Resolve directly from src to dst. */
si_blitter_begin(ctx, SI_COLOR_RESOLVE |
(info->render_condition_enable ? 0 :
SI_DISABLE_RENDER_COND));
util_blitter_custom_resolve_color(sctx->blitter,
info->dst.resource,
info->dst.level,
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 2e62725..8010e59 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -396,21 +396,21 @@ void si_set_mutable_tex_desc_fields(struct r600_texture
*tex,
state[3] &= C_008F1C_TILING_INDEX;
state[4] &= C_008F20_PITCH;
state[6] &= C_008F28_COMPRESSION_EN;
state[0] = va >> 8;
state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level,
is_stencil));
state[4] |= S_008F20_PITCH(pitch - 1);
- if (tex->dcc_offset && first_level < tex->surface.num_dcc_levels) {
+ if (vi_dcc_enabled(tex, first_level)) {
state[6] |= S_008F28_COMPRESSION_EN(1);
state[7] = ((!tex->dcc_separate_buffer ?
tex->resource.gpu_address : 0) +
tex->dcc_offset +
base_level_info->dcc_offset) >> 8;
} else if (tex->tc_compatible_htile) {
state[6] |= S_008F28_COMPRESSION_EN(1);
state[7] = tex->htile_buffer->gpu_address >> 8;
}
}
@@ -692,22 +692,21 @@ static void si_set_shader_image(struct si_context *ctx,
descs->list + slot * 8);
si_set_buf_desc_address(res, view->u.buf.offset, desc + 4);
images->compressed_colortex_mask &= ~(1 << slot);
res->bind_history |= PIPE_BIND_SHADER_IMAGE;
} else {
static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
struct r600_texture *tex = (struct r600_texture *)res;
unsigned level = view->u.tex.level;
unsigned width, height, depth;
- bool uses_dcc = tex->dcc_offset &&
- level < tex->surface.num_dcc_levels;
+ bool uses_dcc = vi_dcc_enabled(tex, level);
assert(!tex->is_depth);
assert(tex->fmask.size == 0);
if (uses_dcc && !skip_decompress &&
(view->access & PIPE_IMAGE_ACCESS_WRITE ||
!vi_dcc_formats_compatible(res->b.b.format,
view->format))) {
/* If DCC can't be disabled, at least decompress it.
* The decompression is relatively cheap if the surface
* has been decompressed already.
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 0ee4af3..eed7752 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2582,21 +2582,21 @@ static void si_emit_framebuffer_state(struct si_context
*sctx, struct r600_atom
/* This must be set for fast clear to work without
FMASK. */
if (sctx->b.chip_class >= CIK)
cb_color_pitch |=
S_028C64_FMASK_TILE_MAX(pitch_tile_max);
cb_color_attrib |=
S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
cb_color_fmask = cb_color_base;
cb_color_fmask_slice =
S_028C88_TILE_MAX(slice_tile_max);
}
cb_color_info = cb->cb_color_info | tex->cb_color_info;
- if (tex->dcc_offset && cb->base.u.tex.level <
tex->surface.num_dcc_levels) {
+ if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
bool is_msaa_resolve_dst = state->cbufs[0] &&
state->cbufs[0]->texture->nr_samples > 1 &&
state->cbufs[1] == &cb->base
&&
state->cbufs[1]->texture->nr_samples <= 1;
if (!is_msaa_resolve_dst)
cb_color_info |= S_028C70_DCC_ENABLE(1);
}
radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i *
0x3C,
--
2.7.4
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