From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/si_descriptors.c | 14 +++++++++++---
src/gallium/drivers/radeonsi/si_pipe.h | 1 +
src/gallium/drivers/radeonsi/si_state.c | 7 ++++---
3 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 8010e59..9b1d1f4 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -422,47 +422,55 @@ static void si_set_sampler_view(struct si_context *sctx,
struct si_sampler_views *views = &sctx->samplers[shader].views;
struct si_sampler_view *rview = (struct si_sampler_view*)view;
struct si_descriptors *descs = si_sampler_descriptors(sctx, shader);
uint32_t *desc = descs->list + slot * 16;
if (views->views[slot] == view && !disallow_early_out)
return;
if (view) {
struct r600_texture *rtex = (struct r600_texture
*)view->texture;
+ bool is_buffer = rtex->resource.b.b.target == PIPE_BUFFER;
+
+ if (unlikely(!is_buffer && rview->dcc_incompatible)) {
+ vi_disable_dcc_if_incompatible_flag(&sctx->b,
+ &rtex->resource.b.b,
+
view->u.tex.first_level,
+
rview->dcc_incompatible);
+ rview->dcc_incompatible = false;
+ }
assert(rtex); /* views with texture == NULL aren't supported */
pipe_sampler_view_reference(&views->views[slot], view);
memcpy(desc, rview->state, 8*4);
- if (rtex->resource.b.b.target == PIPE_BUFFER) {
+ if (is_buffer) {
rtex->resource.bind_history |= PIPE_BIND_SAMPLER_VIEW;
si_set_buf_desc_address(&rtex->resource,
view->u.buf.offset,
desc + 4);
} else {
bool is_separate_stencil =
rtex->db_compatible &&
rview->is_stencil_sampler;
si_set_mutable_tex_desc_fields(rtex,
rview->base_level_info,
rview->base_level,
rview->base.u.tex.first_level,
rview->block_width,
is_separate_stencil,
desc);
}
- if (rtex->resource.b.b.target != PIPE_BUFFER &&
- rtex->fmask.size) {
+ if (!is_buffer && rtex->fmask.size) {
memcpy(desc + 8,
rview->fmask_state, 8*4);
} else {
/* Disable FMASK and bind sampler state in [12:15]. */
memcpy(desc + 8,
null_texture_descriptor, 4*4);
if (views->sampler_states[slot])
memcpy(desc + 12,
views->sampler_states[slot]->val, 4*4);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index 617ec20..d1a8393 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -120,20 +120,21 @@ struct si_blend_color {
struct si_sampler_view {
struct pipe_sampler_view base;
/* [0..7] = image descriptor
* [4..7] = buffer descriptor */
uint32_t state[8];
uint32_t fmask_state[8];
const struct radeon_surf_level *base_level_info;
unsigned base_level;
unsigned block_width;
bool is_stencil_sampler;
+ bool dcc_incompatible;
};
#define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
struct si_sampler_state {
#ifdef DEBUG
unsigned magic;
#endif
uint32_t val[4];
};
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 39b9152..23b6473 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3185,23 +3185,24 @@ si_create_sampler_view_custom(struct pipe_context *ctx,
case PIPE_FORMAT_X24S8_UINT:
case PIPE_FORMAT_S8X24_UINT:
case PIPE_FORMAT_X32_S8X24_UINT:
pipe_format = PIPE_FORMAT_S8_UINT;
surflevel = tmp->surface.stencil_level;
break;
default:;
}
}
- vi_disable_dcc_if_incompatible_format(&sctx->b, texture,
- state->u.tex.first_level,
- state->format);
+ view->dcc_incompatible =
+ vi_dcc_formats_are_incompatible(texture,
+ state->u.tex.first_level,
+ state->format);
si_make_texture_descriptor(sctx->screen, tmp, true,
state->target, pipe_format, state_swizzle,
first_level, last_level,
state->u.tex.first_layer, last_layer,
width, height, depth,
view->state, view->fmask_state);
view->base_level_info = &surflevel[base_level];
view->base_level = base_level;
--
2.7.4
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