From: Marek Olšák <marek.ol...@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
---
src/gallium/drivers/radeon/r600_texture.c | 8 ++++----
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 7 +++++++
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index 77e9bec..d811a77 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -2632,24 +2632,20 @@ void evergreen_do_fast_color_clear(struct
r600_common_context *rctx,
int i;
/* This function is broken in BE, so just disable this path for now */
#ifdef PIPE_ARCH_BIG_ENDIAN
return;
#endif
if (rctx->render_cond)
return;
- /* TODO: fix CMASK and DCC fast clear */
- if (rctx->chip_class >= GFX9)
- return;
-
for (i = 0; i < fb->nr_cbufs; i++) {
struct r600_texture *tex;
unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
if (!fb->cbufs[i])
continue;
/* if this colorbuffer is not being cleared */
if (!(*buffers & clear_bit))
continue;
@@ -2703,20 +2699,24 @@ void evergreen_do_fast_color_clear(struct
r600_common_context *rctx,
if (tex->dcc_gather_statistics &&
rctx->screen->rbplus_allowed)
tex->num_slow_clears++;
}
/* Try to clear DCC first, otherwise try CMASK. */
if (vi_dcc_enabled(tex, 0)) {
uint32_t reset_value;
bool clear_words_needed;
+ /* TODO: fix DCC clear */
+ if (rctx->chip_class >= GFX9)
+ continue;
+
if (rctx->screen->debug_flags & DBG_NO_DCC_CLEAR)
continue;
if (!vi_get_fast_clear_parameters(fb->cbufs[i]->format,
color, &reset_value,
&clear_words_needed))
continue;
vi_dcc_clear_level(rctx, tex, 0, reset_value);
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 1e63d64..4d532e3 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -648,20 +648,27 @@ static int gfx9_compute_miptree(struct amdgpu_winsys *ws,
out.mipChainPitch - 1;
surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
return 0;
}
surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
out.mipChainPitch - 1;
+
+ /* CMASK fast clear uses these even if FMASK isn't allocated.
+ * FMASK only supports the Z swizzle modes, whose numbers are multiples of
4.
+ */
+ surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
+ surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
+
surf->u.gfx9.surf_slice_size = out.sliceSize;
surf->u.gfx9.surf_pitch = out.pitch;
surf->u.gfx9.surf_height = out.height;
surf->surf_size = out.surfSize;
surf->surf_alignment = out.baseAlign;
if (in->swizzleMode == ADDR_SW_LINEAR) {
for (unsigned i = 0; i < in->numMipLevels; i++)
surf->u.gfx9.offset[i] = mip_info[i].offset;
}
--
2.7.4
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