From: Marek Olšák <marek.ol...@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
---
src/gallium/drivers/radeonsi/si_shader.c | 5 ++---
src/gallium/drivers/radeonsi/si_state.c | 3 +--
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 2 +-
3 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 580781bd..d4f37365 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -4583,23 +4583,22 @@ static void tex_fetch_args(
* should be fetched to get that sample.
*
* For example, 0x11111100 means there are only 2 samples stored and
* the second sample covers 3/4 of the pixel. When reading samples 0
* and 1, return physical sample 0 (determined by the first two 0s
* in FMASK), otherwise return physical sample 1.
*
* The sample index should be adjusted as follows:
* sample_index = (fmask >> (sample_index * 4)) & 0xF;
*/
- if (ctx->screen->b.chip_class <= VI && /* TODO: fix FMASK on GFX9 */
- (target == TGSI_TEXTURE_2D_MSAA ||
- target == TGSI_TEXTURE_2D_ARRAY_MSAA)) {
+ if (target == TGSI_TEXTURE_2D_MSAA ||
+ target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
struct lp_build_context *uint_bld = &bld_base->uint_bld;
struct lp_build_emit_data txf_emit_data = *emit_data;
LLVMValueRef txf_address[4];
/* We only need .xy for non-arrays, and .xyz for arrays. */
unsigned txf_count = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
struct tgsi_full_instruction inst = {};
memcpy(txf_address, address, sizeof(txf_address));
/* Read FMASK using TXF_LZ. */
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 78d6996..35fadec 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2191,22 +2191,21 @@ static void si_initialize_color_surface(struct
si_context *sctx,
color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
PIPE_SWIZZLE_1 ||
util_format_is_intensity(surf->base.format));
if (rtex->resource.b.b.nr_samples > 1) {
unsigned log_samples =
util_logbase2(rtex->resource.b.b.nr_samples);
color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
S_028C74_NUM_FRAGMENTS(log_samples);
if (rtex->fmask.size) {
- /* TODO: fix FMASK on GFX9: */
- color_info |= S_028C70_COMPRESSION(sctx->b.chip_class
<= VI);
+ color_info |= S_028C70_COMPRESSION(1);
unsigned fmask_bankh =
util_logbase2(rtex->fmask.bank_height);
if (sctx->b.chip_class == SI) {
/* due to a hw bug, FMASK_BANK_HEIGHT must be
set on SI too */
color_attrib |=
S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
}
}
}
surf->cb_color_view = color_view;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 7566087..1e63d64 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -746,21 +746,21 @@ static int gfx9_compute_miptree(struct amdgpu_winsys *ws,
fin.unalignedWidth = in->width;
fin.unalignedHeight = in->height;
fin.numSlices = in->numSlices;
fin.numSamples = in->numSamples;
fin.numFrags = in->numFrags;
ret = Addr2ComputeFmaskInfo(ws->addrlib, &fin, &fout);
if (ret != ADDR_OK)
return ret;
- surf->u.gfx9.fmask.swizzle_mode = in->swizzleMode;
+ surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
surf->u.gfx9.fmask.epitch = fout.pitch - 1;
surf->u.gfx9.fmask_size = fout.fmaskBytes;
surf->u.gfx9.fmask_alignment = fout.baseAlign;
}
/* CMASK */
if (in->swizzleMode != ADDR_SW_LINEAR) {
ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
--
2.7.4
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