From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/si_shader.c | 69 +++++++++++++++++++++--
src/gallium/drivers/radeonsi/si_shader_internal.h | 17 +++---
2 files changed, 74 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 3a785c2..5e1f59c 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -5770,20 +5770,29 @@ static void declare_vs_input_vgprs(struct
si_shader_context *ctx,
if (!shader->is_gs_copy_shader) {
/* Vertex load indices. */
ctx->param_vertex_index0 = (*num_params);
for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
params[(*num_params)++] = ctx->i32;
*num_prolog_vgprs += shader->selector->info.num_inputs;
}
}
+static void declare_tes_input_vgprs(struct si_shader_context *ctx,
+ LLVMTypeRef *params, unsigned *num_params)
+{
+ params[ctx->param_tes_u = (*num_params)++] = ctx->f32;
+ params[ctx->param_tes_v = (*num_params)++] = ctx->f32;
+ params[ctx->param_tes_rel_patch_id = (*num_params)++] = ctx->i32;
+ params[ctx->param_tes_patch_id = (*num_params)++] = ctx->i32;
+}
+
enum {
/* Convenient merged shader definitions. */
SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
};
static void create_function(struct si_shader_context *ctx)
{
struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
struct gallivm_state *gallivm = &ctx->gallivm;
@@ -5907,44 +5916,94 @@ static void create_function(struct si_shader_context
*ctx)
* should be passed to the epilog.
*/
for (i = 0; i <= 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT; i++)
returns[num_returns++] = ctx->i32; /* SGPRs */
for (i = 0; i < 3; i++)
returns[num_returns++] = ctx->f32; /* VGPRs */
}
break;
case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
- assert(!"unimplemented merged ES-GS shader");
+ /* Merged stages have 8 system SGPRs at the beginning. */
+ params[ctx->param_rw_buffers = num_params++] = /*
SPI_SHADER_USER_DATA_ADDR_LO_GS */
+ const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
+ params[ctx->param_gs2vs_offset = num_params++] = ctx->i32;
+ params[ctx->param_merged_wave_info = num_params++] = ctx->i32;
+ params[ctx->param_tcs_offchip_offset = num_params++] = ctx->i32;
+ params[ctx->param_merged_scratch_offset = num_params++] =
ctx->i32;
+ params[num_params++] = ctx->i32; /* unused
(SPI_SHADER_PGM_LO/HI_GS << 8) */
+ params[num_params++] = ctx->i32; /* unused
(SPI_SHADER_PGM_LO/HI_GS >> 24) */
+
+ params[num_params++] = ctx->i32; /* unused */
+ params[num_params++] = ctx->i32; /* unused */
+ declare_per_stage_desc_pointers(ctx, params, &num_params,
+ (ctx->type ==
PIPE_SHADER_VERTEX ||
+ ctx->type ==
PIPE_SHADER_TESS_EVAL));
+ if (ctx->type == PIPE_SHADER_VERTEX) {
+ declare_vs_specific_input_sgprs(ctx, params,
&num_params);
+ } else {
+ /* TESS_EVAL (and also GEOMETRY):
+ * Declare as many input SGPRs as the VS has. */
+ params[ctx->param_tcs_offchip_layout = num_params++] =
ctx->i32;
+ params[num_params++] = ctx->i32; /* unused */
+ params[num_params++] = ctx->i32; /* unused */
+ params[num_params++] = ctx->i32; /* unused */
+ params[num_params++] = ctx->i32; /* unused */
+ params[ctx->param_vs_state_bits = num_params++] =
ctx->i32; /* unused */
+ }
+
+ declare_per_stage_desc_pointers(ctx, params, &num_params,
+ ctx->type ==
PIPE_SHADER_GEOMETRY);
+ last_sgpr = num_params - 1;
+
+ /* VGPRs (first GS, then VS/TES) */
+ params[ctx->param_gs_vtx01_offset = num_params++] = ctx->i32;
+ params[ctx->param_gs_vtx23_offset = num_params++] = ctx->i32;
+ params[ctx->param_gs_prim_id = num_params++] = ctx->i32;
+ params[ctx->param_gs_instance_id = num_params++] = ctx->i32;
+ params[ctx->param_gs_vtx45_offset = num_params++] = ctx->i32;
+
+ if (ctx->type == PIPE_SHADER_VERTEX) {
+ declare_vs_input_vgprs(ctx, params, &num_params,
+ &num_prolog_vgprs);
+ } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
+ declare_tes_input_vgprs(ctx, params, &num_params);
+ }
+
+ if (ctx->type == PIPE_SHADER_VERTEX ||
+ ctx->type == PIPE_SHADER_TESS_EVAL) {
+ /* ES return values are inputs to GS. */
+ for (i = 0; i < 8 + GFX9_GS_NUM_USER_SGPR; i++)
+ returns[num_returns++] = ctx->i32; /* SGPRs */
+ for (i = 0; i < 5; i++)
+ returns[num_returns++] = ctx->f32; /* VGPRs */
+ }
break;
case PIPE_SHADER_TESS_EVAL:
declare_default_desc_pointers(ctx, params, &num_params);
params[ctx->param_tcs_offchip_layout = num_params++] = ctx->i32;
if (shader->key.as_es) {
params[ctx->param_tcs_offchip_offset = num_params++] =
ctx->i32;
params[num_params++] = ctx->i32;
params[ctx->param_es2gs_offset = num_params++] =
ctx->i32;
} else {
params[num_params++] = ctx->i32;
declare_streamout_params(ctx, &shader->selector->so,
params, ctx->i32, &num_params);
params[ctx->param_tcs_offchip_offset = num_params++] =
ctx->i32;
}
last_sgpr = num_params - 1;
/* VGPRs */
- params[ctx->param_tes_u = num_params++] = ctx->f32;
- params[ctx->param_tes_v = num_params++] = ctx->f32;
- params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
- params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
+ declare_tes_input_vgprs(ctx, params, &num_params);
/* PrimitiveID output. */
if (!shader->key.as_es)
for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
returns[num_returns++] = ctx->f32;
break;
case PIPE_SHADER_GEOMETRY:
declare_default_desc_pointers(ctx, params, &num_params);
params[ctx->param_gs2vs_offset = num_params++] = ctx->i32;
diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h
b/src/gallium/drivers/radeonsi/si_shader_internal.h
index c344c16..233a96f 100644
--- a/src/gallium/drivers/radeonsi/si_shader_internal.h
+++ b/src/gallium/drivers/radeonsi/si_shader_internal.h
@@ -169,29 +169,32 @@ struct si_shader_context {
/* API TES */
int param_tes_u;
int param_tes_v;
int param_tes_rel_patch_id;
int param_tes_patch_id;
/* HW ES */
int param_es2gs_offset;
/* API GS */
int param_gs2vs_offset;
- int param_gs_wave_id;
- int param_gs_vtx0_offset;
- int param_gs_vtx1_offset;
+ int param_gs_wave_id; /* GFX6 */
+ int param_gs_vtx0_offset; /* in dwords (GFX6) */
+ int param_gs_vtx1_offset; /* in dwords (GFX6) */
int param_gs_prim_id;
- int param_gs_vtx2_offset;
- int param_gs_vtx3_offset;
- int param_gs_vtx4_offset;
- int param_gs_vtx5_offset;
+ int param_gs_vtx2_offset; /* in dwords (GFX6) */
+ int param_gs_vtx3_offset; /* in dwords (GFX6) */
+ int param_gs_vtx4_offset; /* in dwords (GFX6) */
+ int param_gs_vtx5_offset; /* in dwords (GFX6) */
int param_gs_instance_id;
+ int param_gs_vtx01_offset; /* in dwords (GFX9) */
+ int param_gs_vtx23_offset; /* in dwords (GFX9) */
+ int param_gs_vtx45_offset; /* in dwords (GFX9) */
LLVMTargetMachineRef tm;
unsigned range_md_kind;
unsigned fpmath_md_kind;
LLVMValueRef fpmath_md_2p5_ulp;
/* Preloaded descriptors. */
LLVMValueRef esgs_ring;
LLVMValueRef gsvs_ring[4];
--
2.7.4
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