From: Marek Olšák <marek.ol...@amd.com>
0 is PIPE_QUERY_OCCLUSION_COUNTER, which is not what we want.
---
src/gallium/drivers/radeon/r600_pipe_common.h | 2 ++
src/gallium/drivers/radeonsi/si_perfcounter.c | 2 +-
src/gallium/drivers/radeonsi/si_state_draw.c | 4 ++--
3 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 5a968a4..7a311ea 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -57,20 +57,22 @@
#define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
/* Pipeline & streamout query controls. */
#define R600_CONTEXT_START_PIPELINE_STATS (1u << 1)
#define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2)
#define R600_CONTEXT_PRIVATE_FLAG (1u << 3)
/* special primitive types */
#define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
+#define R600_NOT_QUERY 0xffffffff
+
/* Debug flags. */
/* logging and features */
#define DBG_TEX (1 << 0)
#define DBG_NIR (1 << 1)
#define DBG_COMPUTE (1 << 2)
#define DBG_VM (1 << 3)
/* gap */
/* shader logging */
#define DBG_FS (1 << 5)
#define DBG_VS (1 << 6)
diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c
b/src/gallium/drivers/radeonsi/si_perfcounter.c
index 531d3b7..cb67fd2 100644
--- a/src/gallium/drivers/radeonsi/si_perfcounter.c
+++ b/src/gallium/drivers/radeonsi/si_perfcounter.c
@@ -584,21 +584,21 @@ static void si_pc_emit_start(struct r600_common_context
*ctx,
}
/* Note: The buffer was already added in si_pc_emit_start, so we don't have to
* do it again in here. */
static void si_pc_emit_stop(struct r600_common_context *ctx,
struct r600_resource *buffer, uint64_t va)
{
struct radeon_winsys_cs *cs = ctx->gfx.cs;
r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0, 1,
- buffer, va, 0, 0);
+ buffer, va, 0, R600_NOT_QUERY);
r600_gfx_wait_fence(ctx, va, 0, 0xffffffff);
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PERFCOUNTER_SAMPLE) |
EVENT_INDEX(0));
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PERFCOUNTER_STOP) |
EVENT_INDEX(0));
radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
S_036020_PERFMON_STATE(V_036020_STOP_COUNTING) |
S_036020_PERFMON_SAMPLE_ENABLE(1));
}
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index db8f77d..1de8eaa 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -891,21 +891,21 @@ void si_emit_cache_flush(struct si_context *sctx)
S_0085F0_CB2_DEST_BASE_ENA(1) |
S_0085F0_CB3_DEST_BASE_ENA(1) |
S_0085F0_CB4_DEST_BASE_ENA(1) |
S_0085F0_CB5_DEST_BASE_ENA(1) |
S_0085F0_CB6_DEST_BASE_ENA(1) |
S_0085F0_CB7_DEST_BASE_ENA(1);
/* Necessary for DCC */
if (rctx->chip_class == VI)
r600_gfx_write_event_eop(rctx,
V_028A90_FLUSH_AND_INV_CB_DATA_TS,
- 0, 0, NULL, 0, 0, 0);
+ 0, 0, NULL, 0, 0,
R600_NOT_QUERY);
}
if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB)
cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
S_0085F0_DB_DEST_BASE_ENA(1);
}
if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
/* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
EVENT_INDEX(0));
@@ -992,21 +992,21 @@ void si_emit_cache_flush(struct si_context *sctx)
SI_CONTEXT_INV_VMEM_L1);
sctx->b.num_L2_invalidates++;
}
/* Do the flush (enqueue the event and wait for it). */
va = sctx->wait_mem_scratch->gpu_address;
sctx->wait_mem_number++;
r600_gfx_write_event_eop(rctx, cb_db_event, tc_flags, 1,
sctx->wait_mem_scratch, va,
- sctx->wait_mem_number, 0);
+ sctx->wait_mem_number, R600_NOT_QUERY);
r600_gfx_wait_fence(rctx, va, sctx->wait_mem_number,
0xffffffff);
}
/* Make sure ME is idle (it executes most packets) before continuing.
* This prevents read-after-write hazards between PFP and ME.
*/
if (cp_coher_cntl ||
(rctx->flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
SI_CONTEXT_INV_VMEM_L1 |
SI_CONTEXT_INV_GLOBAL_L2 |
--
2.7.4
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