From: Marek Olšák <[email protected]>
---
src/amd/common/r600d_common.h | 165 ----------------------
src/amd/common/sid.h | 17 +++
src/amd/vulkan/radv_cmd_buffer.c | 6 +-
src/amd/vulkan/radv_pipeline.c | 6 +-
src/amd/vulkan/si_cmd_buffer.c | 28 ++--
src/gallium/drivers/r600/cayman_msaa.c | 1 +
src/gallium/drivers/r600/evergreen_state.c | 4 +-
src/gallium/drivers/r600/evergreend.h | 110 +++++++++++++++
src/gallium/drivers/r600/r600_streamout.c | 14 +-
src/gallium/drivers/r600/r600_viewport.c | 23 +++
src/gallium/drivers/radeon/r600_cs.h | 14 +-
src/gallium/drivers/radeon/r600_perfcounter.c | 2 +-
src/gallium/drivers/radeon/r600_pipe_common.c | 1 +
src/gallium/drivers/radeon/r600_query.c | 21 +--
src/gallium/drivers/radeon/r600_texture.c | 35 ++---
src/gallium/drivers/radeonsi/si_perfcounter.c | 8 +-
src/gallium/drivers/radeonsi/si_state.c | 26 ++--
src/gallium/drivers/radeonsi/si_state_msaa.c | 28 ++--
src/gallium/drivers/radeonsi/si_state_streamout.c | 4 +-
19 files changed, 252 insertions(+), 261 deletions(-)
diff --git a/src/amd/common/r600d_common.h b/src/amd/common/r600d_common.h
index 76c5c4f..ed1d460 100644
--- a/src/amd/common/r600d_common.h
+++ b/src/amd/common/r600d_common.h
@@ -32,22 +32,20 @@
#define SI_SH_REG_END 0x0000C000
#define CIK_UCONFIG_REG_OFFSET 0x00030000
#define CIK_UCONFIG_REG_END 0x00038000
#define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
#define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
#define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8)
#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) |
PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
-#define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
-
#define PKT3_NOP 0x10
#define PKT3_SET_PREDICATION 0x20
#define PKT3_STRMOUT_BUFFER_UPDATE 0x34
#define STRMOUT_STORE_BUFFER_FILLED_SIZE 1
#define STRMOUT_OFFSET_SOURCE(x) (((unsigned)(x) & 0x3)
<< 1)
#define STRMOUT_OFFSET_FROM_PACKET 0
#define STRMOUT_OFFSET_FROM_VGT_FILLED_SIZE 1
#define STRMOUT_OFFSET_FROM_MEM 2
#define STRMOUT_OFFSET_NONE 3
#define STRMOUT_SELECT_BUFFER(x) (((unsigned)(x) & 0x3)
<< 8)
@@ -119,182 +117,19 @@
#define PREDICATION_OP_ZPASS 0x1
#define PREDICATION_OP_PRIMCOUNT 0x2
#define PREDICATION_OP_BOOL64 0x3
#define PRED_OP(x) ((x) << 16)
#define PREDICATION_CONTINUE (1 << 31)
#define PREDICATION_HINT_WAIT (0 << 12)
#define PREDICATION_HINT_NOWAIT_DRAW (1 << 12)
#define PREDICATION_DRAW_NOT_VISIBLE (0 << 8)
#define PREDICATION_DRAW_VISIBLE (1 << 8)
-/* R600-R700*/
-#define R_008490_CP_STRMOUT_CNTL 0x008490
-#define S_008490_OFFSET_UPDATE_DONE(x) (((unsigned)(x) & 0x1)
<< 0)
-#define R_028AB0_VGT_STRMOUT_EN 0x028AB0
-#define S_028AB0_STREAMOUT(x) (((unsigned)(x) & 0x1)
<< 0)
-#define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1)
-#define C_028AB0_STREAMOUT 0xFFFFFFFE
-#define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20
-#define S_028B20_BUFFER_0_EN(x) (((unsigned)(x) & 0x1)
<< 0)
-#define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1)
-#define C_028B20_BUFFER_0_EN 0xFFFFFFFE
-#define S_028B20_BUFFER_1_EN(x) (((unsigned)(x) & 0x1)
<< 1)
-#define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1)
-#define C_028B20_BUFFER_1_EN 0xFFFFFFFD
-#define S_028B20_BUFFER_2_EN(x) (((unsigned)(x) & 0x1)
<< 2)
-#define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1)
-#define C_028B20_BUFFER_2_EN 0xFFFFFFFB
-#define S_028B20_BUFFER_3_EN(x) (((unsigned)(x) & 0x1)
<< 3)
-#define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1)
-#define C_028B20_BUFFER_3_EN 0xFFFFFFF7
-#define R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
0x028AD0
-
#define V_0280A0_SWAP_STD 0x00000000
#define V_0280A0_SWAP_ALT 0x00000001
#define V_0280A0_SWAP_STD_REV 0x00000002
#define V_0280A0_SWAP_ALT_REV 0x00000003
-/* EG+ */
-#define R_0084FC_CP_STRMOUT_CNTL 0x0084FC
-#define S_0084FC_OFFSET_UPDATE_DONE(x) (((unsigned)(x) & 0x1)
<< 0)
-#define R_028B94_VGT_STRMOUT_CONFIG
0x028B94
-#define S_028B94_STREAMOUT_0_EN(x)
(((unsigned)(x) & 0x1) << 0)
-#define G_028B94_STREAMOUT_0_EN(x) (((x) >>
0) & 0x1)
-#define C_028B94_STREAMOUT_0_EN
0xFFFFFFFE
-#define S_028B94_STREAMOUT_1_EN(x)
(((unsigned)(x) & 0x1) << 1)
-#define G_028B94_STREAMOUT_1_EN(x) (((x) >>
1) & 0x1)
-#define C_028B94_STREAMOUT_1_EN
0xFFFFFFFD
-#define S_028B94_STREAMOUT_2_EN(x)
(((unsigned)(x) & 0x1) << 2)
-#define G_028B94_STREAMOUT_2_EN(x) (((x) >>
2) & 0x1)
-#define C_028B94_STREAMOUT_2_EN
0xFFFFFFFB
-#define S_028B94_STREAMOUT_3_EN(x)
(((unsigned)(x) & 0x1) << 3)
-#define G_028B94_STREAMOUT_3_EN(x) (((x) >>
3) & 0x1)
-#define C_028B94_STREAMOUT_3_EN
0xFFFFFFF7
-#define S_028B94_RAST_STREAM(x)
(((unsigned)(x) & 0x07) << 4)
-#define G_028B94_RAST_STREAM(x) (((x) >>
4) & 0x07)
-#define C_028B94_RAST_STREAM
0xFFFFFF8F
-#define S_028B94_RAST_STREAM_MASK(x)
(((unsigned)(x) & 0x0F) << 8) /* SI+ */
-#define G_028B94_RAST_STREAM_MASK(x) (((x) >>
8) & 0x0F)
-#define C_028B94_RAST_STREAM_MASK
0xFFFFF0FF
-#define S_028B94_USE_RAST_STREAM_MASK(x)
(((unsigned)(x) & 0x1) << 31) /* SI+ */
-#define G_028B94_USE_RAST_STREAM_MASK(x) (((x) >>
31) & 0x1)
-#define C_028B94_USE_RAST_STREAM_MASK
0x7FFFFFFF
-#define R_028B98_VGT_STRMOUT_BUFFER_CONFIG
0x028B98
-#define S_028B98_STREAM_0_BUFFER_EN(x)
(((unsigned)(x) & 0x0F) << 0)
-#define G_028B98_STREAM_0_BUFFER_EN(x) (((x) >>
0) & 0x0F)
-#define C_028B98_STREAM_0_BUFFER_EN
0xFFFFFFF0
-#define S_028B98_STREAM_1_BUFFER_EN(x)
(((unsigned)(x) & 0x0F) << 4)
-#define G_028B98_STREAM_1_BUFFER_EN(x) (((x) >>
4) & 0x0F)
-#define C_028B98_STREAM_1_BUFFER_EN
0xFFFFFF0F
-#define S_028B98_STREAM_2_BUFFER_EN(x)
(((unsigned)(x) & 0x0F) << 8)
-#define G_028B98_STREAM_2_BUFFER_EN(x) (((x) >>
8) & 0x0F)
-#define C_028B98_STREAM_2_BUFFER_EN
0xFFFFF0FF
-#define S_028B98_STREAM_3_BUFFER_EN(x)
(((unsigned)(x) & 0x0F) << 12)
-#define G_028B98_STREAM_3_BUFFER_EN(x) (((x) >>
12) & 0x0F)
-#define C_028B98_STREAM_3_BUFFER_EN
0xFFFF0FFF
-
-#define EG_R_028A4C_PA_SC_MODE_CNTL_1 0x028A4C
-#define EG_S_028A4C_PS_ITER_SAMPLE(x) (((unsigned)(x) & 0x1)
<< 16)
-#define EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((unsigned)(x) & 0x1)
<< 25)
-#define EG_S_028A4C_FORCE_EOV_REZ_ENABLE(x) (((unsigned)(x) & 0x1)
<< 26)
-
-#define CM_R_028804_DB_EQAA 0x00028804
-#define S_028804_MAX_ANCHOR_SAMPLES(x) (((unsigned)(x) &
0x07) << 0)
-#define G_028804_MAX_ANCHOR_SAMPLES(x) (((x) >> 0) & 0x07)
-#define C_028804_MAX_ANCHOR_SAMPLES 0xFFFFFFF8
-#define S_028804_PS_ITER_SAMPLES(x) (((unsigned)(x) &
0x07) << 4)
-#define G_028804_PS_ITER_SAMPLES(x) (((x) >> 4) & 0x07)
-#define C_028804_PS_ITER_SAMPLES 0xFFFFFF8F
-#define S_028804_MASK_EXPORT_NUM_SAMPLES(x) (((unsigned)(x) &
0x07) << 8)
-#define G_028804_MASK_EXPORT_NUM_SAMPLES(x) (((x) >> 8) & 0x07)
-#define C_028804_MASK_EXPORT_NUM_SAMPLES 0xFFFFF8FF
-#define S_028804_ALPHA_TO_MASK_NUM_SAMPLES(x) (((unsigned)(x) &
0x07) << 12)
-#define G_028804_ALPHA_TO_MASK_NUM_SAMPLES(x) (((x) >> 12) & 0x07)
-#define C_028804_ALPHA_TO_MASK_NUM_SAMPLES 0xFFFF8FFF
-#define S_028804_HIGH_QUALITY_INTERSECTIONS(x) (((unsigned)(x) & 0x1)
<< 16)
-#define G_028804_HIGH_QUALITY_INTERSECTIONS(x) (((x) >> 16) & 0x1)
-#define C_028804_HIGH_QUALITY_INTERSECTIONS 0xFFFEFFFF
-#define S_028804_INCOHERENT_EQAA_READS(x) (((unsigned)(x) & 0x1)
<< 17)
-#define G_028804_INCOHERENT_EQAA_READS(x) (((x) >> 17) & 0x1)
-#define C_028804_INCOHERENT_EQAA_READS 0xFFFDFFFF
-#define S_028804_INTERPOLATE_COMP_Z(x) (((unsigned)(x) & 0x1)
<< 18)
-#define G_028804_INTERPOLATE_COMP_Z(x) (((x) >> 18) & 0x1)
-#define C_028804_INTERPOLATE_COMP_Z 0xFFFBFFFF
-#define S_028804_INTERPOLATE_SRC_Z(x) (((unsigned)(x) & 0x1)
<< 19)
-#define G_028804_INTERPOLATE_SRC_Z(x) (((x) >> 19) & 0x1)
-#define C_028804_INTERPOLATE_SRC_Z 0xFFF7FFFF
-#define S_028804_STATIC_ANCHOR_ASSOCIATIONS(x) (((unsigned)(x) & 0x1)
<< 20)
-#define G_028804_STATIC_ANCHOR_ASSOCIATIONS(x) (((x) >> 20) & 0x1)
-#define C_028804_STATIC_ANCHOR_ASSOCIATIONS 0xFFEFFFFF
-#define S_028804_ALPHA_TO_MASK_EQAA_DISABLE(x) (((unsigned)(x) & 0x1)
<< 21)
-#define G_028804_ALPHA_TO_MASK_EQAA_DISABLE(x) (((x) >> 21) & 0x1)
-#define C_028804_ALPHA_TO_MASK_EQAA_DISABLE 0xFFDFFFFF
-#define S_028804_OVERRASTERIZATION_AMOUNT(x) (((unsigned)(x) &
0x07) << 24)
-#define G_028804_OVERRASTERIZATION_AMOUNT(x) (((x) >> 24) & 0x07)
-#define C_028804_OVERRASTERIZATION_AMOUNT 0xF8FFFFFF
-#define S_028804_ENABLE_POSTZ_OVERRASTERIZATION(x) (((unsigned)(x) & 0x1)
<< 27)
-#define G_028804_ENABLE_POSTZ_OVERRASTERIZATION(x) (((x) >> 27) & 0x1)
-#define C_028804_ENABLE_POSTZ_OVERRASTERIZATION 0xF7FFFFFF
-#define CM_R_028BDC_PA_SC_LINE_CNTL 0x28bdc
-#define S_028BDC_EXPAND_LINE_WIDTH(x) (((unsigned)(x) & 0x1)
<< 9)
-#define G_028BDC_EXPAND_LINE_WIDTH(x) (((x) >> 9) & 0x1)
-#define C_028BDC_EXPAND_LINE_WIDTH 0xFFFFFDFF
-#define S_028BDC_LAST_PIXEL(x) (((unsigned)(x) & 0x1)
<< 10)
-#define G_028BDC_LAST_PIXEL(x) (((x) >> 10) & 0x1)
-#define C_028BDC_LAST_PIXEL 0xFFFFFBFF
-#define S_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((unsigned)(x) & 0x1)
<< 11)
-#define G_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((x) >> 11) & 0x1)
-#define C_028BDC_PERPENDICULAR_ENDCAP_ENA 0xFFFFF7FF
-#define S_028BDC_DX10_DIAMOND_TEST_ENA(x) (((unsigned)(x) & 0x1)
<< 12)
-#define G_028BDC_DX10_DIAMOND_TEST_ENA(x) (((x) >> 12) & 0x1)
-#define C_028BDC_DX10_DIAMOND_TEST_ENA 0xFFFFEFFF
-#define CM_R_028BE0_PA_SC_AA_CONFIG 0x28be0
-#define S_028BE0_MSAA_NUM_SAMPLES(x) (((unsigned)(x) & 0x07)
<< 0)
-#define G_028BE0_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x07)
-#define C_028BE0_MSAA_NUM_SAMPLES 0xFFFFFFF8
-#define S_028BE0_AA_MASK_CENTROID_DTMN(x) (((unsigned)(x) & 0x1)
<< 4)
-#define G_028BE0_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1)
-#define C_028BE0_AA_MASK_CENTROID_DTMN 0xFFFFFFEF
-#define S_028BE0_MAX_SAMPLE_DIST(x) (((unsigned)(x) & 0x0F)
<< 13)
-#define G_028BE0_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0x0F)
-#define C_028BE0_MAX_SAMPLE_DIST 0xFFFE1FFF
-#define S_028BE0_MSAA_EXPOSED_SAMPLES(x) (((unsigned)(x) & 0x07)
<< 20)
-#define G_028BE0_MSAA_EXPOSED_SAMPLES(x) (((x) >> 20) & 0x07)
-#define C_028BE0_MSAA_EXPOSED_SAMPLES 0xFF8FFFFF
-#define S_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((unsigned)(x) & 0x03)
<< 24)
-#define G_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((x) >> 24) & 0x03)
-#define C_028BE0_DETAIL_TO_EXPOSED_MODE 0xFCFFFFFF
-#define CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x28bf8
-#define CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x28c08
-#define CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x28c18
-#define CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x28c28
-
#define EG_S_028C70_FAST_CLEAR(x) (((unsigned)(x) &
0x1) << 17)
#define SI_S_028C70_FAST_CLEAR(x) (((unsigned)(x) &
0x1) << 13)
-/*CIK+*/
-#define R_0300FC_CP_STRMOUT_CNTL 0x0300FC
-
-#define R600_R_028C0C_PA_CL_GB_VERT_CLIP_ADJ 0x028C0C
-#define CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ 0x28be8
-#define R_02843C_PA_CL_VPORT_XSCALE 0x02843C
-
-#define R_028250_PA_SC_VPORT_SCISSOR_0_TL
0x028250
-#define S_028250_TL_X(x)
(((unsigned)(x) & 0x7FFF) << 0)
-#define G_028250_TL_X(x) (((x) >>
0) & 0x7FFF)
-#define C_028250_TL_X
0xFFFF8000
-#define S_028250_TL_Y(x)
(((unsigned)(x) & 0x7FFF) << 16)
-#define G_028250_TL_Y(x) (((x) >>
16) & 0x7FFF)
-#define C_028250_TL_Y
0x8000FFFF
-#define S_028250_WINDOW_OFFSET_DISABLE(x)
(((unsigned)(x) & 0x1) << 31)
-#define G_028250_WINDOW_OFFSET_DISABLE(x) (((x) >>
31) & 0x1)
-#define C_028250_WINDOW_OFFSET_DISABLE
0x7FFFFFFF
-#define S_028254_BR_X(x)
(((unsigned)(x) & 0x7FFF) << 0)
-#define G_028254_BR_X(x) (((x) >>
0) & 0x7FFF)
-#define C_028254_BR_X
0xFFFF8000
-#define S_028254_BR_Y(x)
(((unsigned)(x) & 0x7FFF) << 16)
-#define G_028254_BR_Y(x) (((x) >>
16) & 0x7FFF)
-#define C_028254_BR_Y
0x8000FFFF
-#define R_0282D0_PA_SC_VPORT_ZMIN_0
0x0282D0
-#define R_0282D4_PA_SC_VPORT_ZMAX_0
0x0282D4
-
#endif
diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h
index 1016f67..15ebd9b 100644
--- a/src/amd/common/sid.h
+++ b/src/amd/common/sid.h
@@ -106,20 +106,27 @@
#define R_2C3_DRAW_INDEX_LOC 0x2C3
#define S_2C3_COUNT_INDIRECT_ENABLE(x) (((unsigned)(x) & 0x1) << 30)
#define S_2C3_DRAW_INDEX_ENABLE(x) (((unsigned)(x) & 0x1) << 31)
#define PKT3_DRAW_INDEX_AUTO 0x2D
#define PKT3_DRAW_INDEX_IMMD 0x2E /* not on CIK */
#define PKT3_NUM_INSTANCES 0x2F
#define PKT3_DRAW_INDEX_MULTI_AUTO 0x30
#define PKT3_INDIRECT_BUFFER_SI 0x32 /* not on CIK */
#define PKT3_INDIRECT_BUFFER_CONST 0x33
#define PKT3_STRMOUT_BUFFER_UPDATE 0x34
+#define STRMOUT_STORE_BUFFER_FILLED_SIZE 1
+#define STRMOUT_OFFSET_SOURCE(x) (((unsigned)(x) & 0x3)
<< 1)
+#define STRMOUT_OFFSET_FROM_PACKET 0
+#define STRMOUT_OFFSET_FROM_VGT_FILLED_SIZE 1
+#define STRMOUT_OFFSET_FROM_MEM 2
+#define STRMOUT_OFFSET_NONE 3
+#define STRMOUT_SELECT_BUFFER(x) (((unsigned)(x) & 0x3)
<< 8)
#define PKT3_DRAW_INDEX_OFFSET_2 0x35
#define PKT3_WRITE_DATA 0x37
#define R_370_CONTROL 0x370 /* 0x[packet
number][word index] */
#define S_370_ENGINE_SEL(x) (((unsigned)(x) & 0x3)
<< 30)
#define V_370_ME 0
#define V_370_PFP 1
#define V_370_CE 2
#define V_370_DE 3
#define S_370_WR_CONFIRM(x) (((unsigned)(x) & 0x1)
<< 20)
#define S_370_WR_ONE_ADDR(x) (((unsigned)(x) & 0x1) << 16)
@@ -130,47 +137,57 @@
#define V_370_GDS 3
#define V_370_RESERVED 4
#define V_370_MEM_ASYNC 5
#define R_371_DST_ADDR_LO 0x371
#define R_372_DST_ADDR_HI 0x372
#define PKT3_DRAW_INDEX_INDIRECT_MULTI 0x38
#define PKT3_MEM_SEMAPHORE 0x39
#define PKT3_MPEG_INDEX 0x3A /* not on CIK */
#define PKT3_WAIT_REG_MEM 0x3C
#define WAIT_REG_MEM_EQUAL 3
+#define WAIT_REG_MEM_MEM_SPACE(x) (((unsigned)(x) & 0x3) << 4)
#define PKT3_MEM_WRITE 0x3D /* not on CIK */
#define PKT3_INDIRECT_BUFFER_CIK 0x3F /* new on CIK */
#define R_3F0_IB_BASE_LO 0x3F0
#define R_3F1_IB_BASE_HI 0x3F1
#define R_3F2_CONTROL 0x3F2
#define S_3F2_IB_SIZE(x) (((unsigned)(x) & 0xfffff) << 0)
#define G_3F2_IB_SIZE(x) (((unsigned)(x) >> 0) & 0xfffff)
#define S_3F2_CHAIN(x) (((unsigned)(x) & 0x1) << 20)
#define G_3F2_CHAIN(x) (((unsigned)(x) >> 20) & 0x1)
#define S_3F2_VALID(x) (((unsigned)(x) & 0x1) << 23)
#define PKT3_COPY_DATA 0x40
#define COPY_DATA_SRC_SEL(x) ((x) & 0xf)
#define COPY_DATA_REG 0
#define COPY_DATA_MEM 1
#define COPY_DATA_PERF 4
#define COPY_DATA_IMM 5
#define COPY_DATA_TIMESTAMP 9
#define COPY_DATA_DST_SEL(x) (((unsigned)(x) & 0xf)
<< 8)
+#define COPY_DATA_MEM_ASYNC 5
#define COPY_DATA_COUNT_SEL (1 << 16)
#define COPY_DATA_WR_CONFIRM (1 << 20)
#define PKT3_PFP_SYNC_ME 0x42
#define PKT3_SURFACE_SYNC 0x43 /* deprecated on CIK, use
ACQUIRE_MEM */
#define PKT3_ME_INITIALIZE 0x44 /* not on CIK */
#define PKT3_COND_WRITE 0x45
#define PKT3_EVENT_WRITE 0x46
#define PKT3_EVENT_WRITE_EOP 0x47 /* not on GFX9 */
+#define EOP_INT_SEL(x) ((x) << 24)
+#define EOP_INT_SEL_NONE 0
+#define EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM 3
+#define EOP_DATA_SEL(x) ((x) << 29)
+#define EOP_DATA_SEL_DISCARD 0
+#define EOP_DATA_SEL_VALUE_32BIT 1
+#define EOP_DATA_SEL_VALUE_64BIT 2
+#define EOP_DATA_SEL_TIMESTAMP 3
/* CP DMA bug: Any use of CP_DMA.DST_SEL=TC must be avoided when EOS packets
* are used. Use DST_SEL=MC instead. For prefetch, use SRC_SEL=TC and
* DST_SEL=MC. Only CIK chips are affected.
*/
/* fix CP DMA before uncommenting: */
/*#define PKT3_EVENT_WRITE_EOS 0x48*/ /* not on GFX9 */
#define PKT3_RELEASE_MEM 0x49 /* GFX9+ [any ring] or
GFX8 [compute ring only] */
#define PKT3_ONE_REG_WRITE 0x57 /* not on CIK */
#define PKT3_ACQUIRE_MEM 0x58 /* new for CIK */
#define PKT3_SET_CONFIG_REG 0x68
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 4b41b35..4820cfa 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -525,27 +525,27 @@ radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer,
struct radv_pipeline *pipeline)
{
int num_samples = pipeline->graphics.ms.num_samples;
struct radv_multisample_state *ms = &pipeline->graphics.ms;
struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
radeon_set_context_reg_seq(cmd_buffer->cs,
R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
- radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA,
ms->db_eqaa);
- radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
ms->pa_sc_mode_cntl_1);
+ radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
+ radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1,
ms->pa_sc_mode_cntl_1);
if (old_pipeline && num_samples ==
old_pipeline->graphics.ms.num_samples)
return;
- radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL,
2);
+ radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
/* GFX9: Flush DFSM when the AA mode changes. */
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) |
EVENT_INDEX(0));
}
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 5da2793..60b1d3e 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1063,37 +1063,37 @@ radv_pipeline_init_multisample_state(struct
radv_pipeline *pipeline,
ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
ms->pa_sc_mode_cntl_1 =
S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
/* always 1: */
S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
- EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
- EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
+ S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
+ S_028A4C_FORCE_EOV_REZ_ENABLE(1);
ms->pa_sc_mode_cntl_0 =
S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class
>= GFX9);
if (ms->num_samples > 1) {
unsigned log_samples = util_logbase2(ms->num_samples);
unsigned log_ps_iter_samples =
util_logbase2(util_next_power_of_two(ps_iter_samples));
ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /*
CM_R_028BDC_PA_SC_LINE_CNTL */
ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /*
CM_R_028BE0_PA_SC_AA_CONFIG */
- ms->pa_sc_mode_cntl_1 |=
EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
+ ms->pa_sc_mode_cntl_1 |=
S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
}
const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order =
vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
if (raster_order && raster_order->rasterizationOrder ==
VK_RASTERIZATION_ORDER_RELAXED_AMD) {
ms->pa_sc_mode_cntl_1 |=
S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
}
if (vkms) {
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index f0b3db7..98bbeda 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -1403,56 +1403,56 @@ unsigned radv_cayman_get_maxdist(int log_samples)
cm_max_dist_16x
};
return max_dist[log_samples];
}
void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int
nr_samples)
{
switch (nr_samples) {
default:
case 1:
- radeon_set_context_reg(cs,
CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
- radeon_set_context_reg(cs,
CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
- radeon_set_context_reg(cs,
CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
- radeon_set_context_reg(cs,
CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
+ radeon_set_context_reg(cs,
R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
+ radeon_set_context_reg(cs,
R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
+ radeon_set_context_reg(cs,
R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
+ radeon_set_context_reg(cs,
R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
break;
case 2:
- radeon_set_context_reg(cs,
CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
- radeon_set_context_reg(cs,
CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
- radeon_set_context_reg(cs,
CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
- radeon_set_context_reg(cs,
CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
+ radeon_set_context_reg(cs,
R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
+ radeon_set_context_reg(cs,
R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
+ radeon_set_context_reg(cs,
R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
+ radeon_set_context_reg(cs,
R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
break;
case 4:
- radeon_set_context_reg(cs,
CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
- radeon_set_context_reg(cs,
CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
- radeon_set_context_reg(cs,
CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
- radeon_set_context_reg(cs,
CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
+ radeon_set_context_reg(cs,
R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
+ radeon_set_context_reg(cs,
R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
+ radeon_set_context_reg(cs,
R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
+ radeon_set_context_reg(cs,
R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
break;
case 8:
- radeon_set_context_reg_seq(cs,
CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
+ radeon_set_context_reg_seq(cs,
R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
radeon_emit(cs, cm_sample_locs_8x[0]);
radeon_emit(cs, cm_sample_locs_8x[4]);
radeon_emit(cs, 0);
radeon_emit(cs, 0);
radeon_emit(cs, cm_sample_locs_8x[1]);
radeon_emit(cs, cm_sample_locs_8x[5]);
radeon_emit(cs, 0);
radeon_emit(cs, 0);
radeon_emit(cs, cm_sample_locs_8x[2]);
radeon_emit(cs, cm_sample_locs_8x[6]);
radeon_emit(cs, 0);
radeon_emit(cs, 0);
radeon_emit(cs, cm_sample_locs_8x[3]);
radeon_emit(cs, cm_sample_locs_8x[7]);
break;
case 16:
- radeon_set_context_reg_seq(cs,
CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
+ radeon_set_context_reg_seq(cs,
R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
radeon_emit(cs, cm_sample_locs_16x[0]);
radeon_emit(cs, cm_sample_locs_16x[4]);
radeon_emit(cs, cm_sample_locs_16x[8]);
radeon_emit(cs, cm_sample_locs_16x[12]);
radeon_emit(cs, cm_sample_locs_16x[1]);
radeon_emit(cs, cm_sample_locs_16x[5]);
radeon_emit(cs, cm_sample_locs_16x[9]);
radeon_emit(cs, cm_sample_locs_16x[13]);
radeon_emit(cs, cm_sample_locs_16x[2]);
radeon_emit(cs, cm_sample_locs_16x[6]);
diff --git a/src/gallium/drivers/r600/cayman_msaa.c
b/src/gallium/drivers/r600/cayman_msaa.c
index 33f1040..6bc307a 100644
--- a/src/gallium/drivers/r600/cayman_msaa.c
+++ b/src/gallium/drivers/r600/cayman_msaa.c
@@ -18,20 +18,21 @@
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE
* SOFTWARE.
*
* Authors: Marek Olšák <[email protected]>
*
*/
#include "r600_cs.h"
+#include "evergreend.h"
/* 2xMSAA
* There are two locations (4, 4), (-4, -4). */
const uint32_t eg_sample_locs_2x[4] = {
FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
};
const unsigned eg_max_dist_2x = 4;
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 5e9c77d..4ffc268 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1643,29 +1643,29 @@ static void evergreen_emit_msaa_state(struct
r600_context *rctx, int nr_samples,
max_dist = max_dist_8x;
break;
}
if (nr_samples > 1) {
radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
S_028C00_EXPAND_LINE_WIDTH(1)); /*
R_028C00_PA_SC_LINE_CNTL */
radeon_emit(cs,
S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
S_028C04_MAX_SAMPLE_DIST(max_dist)); /*
R_028C04_PA_SC_AA_CONFIG */
- radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
+ radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
} else {
radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /*
R_028C00_PA_SC_LINE_CNTL */
radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
- radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
+ radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
}
}
static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct
r600_atom *atom)
{
struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
unsigned nr_cbufs = state->nr_cbufs;
diff --git a/src/gallium/drivers/r600/evergreend.h
b/src/gallium/drivers/r600/evergreend.h
index 2e54928..af79bb7 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -194,20 +194,130 @@
/* source is from register */
#define PKT3_SAC_SRC_SEL_REG 0x1
/* source is from GDS offset in CONTROL */
#define PKT3_SAC_SRC_SEL_GDS 0x2
/* source is from memory address */
#define PKT3_SAC_SRC_SEL_MEM 0x3
/* Registers */
#define R_0084FC_CP_STRMOUT_CNTL 0x0084FC
#define S_0084FC_OFFSET_UPDATE_DONE(x) (((unsigned)(x) & 0x1)
<< 0)
+#define R_028B94_VGT_STRMOUT_CONFIG
0x028B94
+#define S_028B94_STREAMOUT_0_EN(x)
(((unsigned)(x) & 0x1) << 0)
+#define G_028B94_STREAMOUT_0_EN(x) (((x) >>
0) & 0x1)
+#define C_028B94_STREAMOUT_0_EN
0xFFFFFFFE
+#define S_028B94_STREAMOUT_1_EN(x)
(((unsigned)(x) & 0x1) << 1)
+#define G_028B94_STREAMOUT_1_EN(x) (((x) >>
1) & 0x1)
+#define C_028B94_STREAMOUT_1_EN
0xFFFFFFFD
+#define S_028B94_STREAMOUT_2_EN(x)
(((unsigned)(x) & 0x1) << 2)
+#define G_028B94_STREAMOUT_2_EN(x) (((x) >>
2) & 0x1)
+#define C_028B94_STREAMOUT_2_EN
0xFFFFFFFB
+#define S_028B94_STREAMOUT_3_EN(x)
(((unsigned)(x) & 0x1) << 3)
+#define G_028B94_STREAMOUT_3_EN(x) (((x) >>
3) & 0x1)
+#define C_028B94_STREAMOUT_3_EN
0xFFFFFFF7
+#define S_028B94_RAST_STREAM(x)
(((unsigned)(x) & 0x07) << 4)
+#define G_028B94_RAST_STREAM(x) (((x) >>
4) & 0x07)
+#define C_028B94_RAST_STREAM
0xFFFFFF8F
+#define S_028B94_RAST_STREAM_MASK(x)
(((unsigned)(x) & 0x0F) << 8) /* SI+ */
+#define G_028B94_RAST_STREAM_MASK(x) (((x) >>
8) & 0x0F)
+#define C_028B94_RAST_STREAM_MASK
0xFFFFF0FF
+#define S_028B94_USE_RAST_STREAM_MASK(x)
(((unsigned)(x) & 0x1) << 31) /* SI+ */
+#define G_028B94_USE_RAST_STREAM_MASK(x) (((x) >>
31) & 0x1)
+#define C_028B94_USE_RAST_STREAM_MASK
0x7FFFFFFF
+#define R_028B98_VGT_STRMOUT_BUFFER_CONFIG
0x028B98
+#define S_028B98_STREAM_0_BUFFER_EN(x)
(((unsigned)(x) & 0x0F) << 0)
+#define G_028B98_STREAM_0_BUFFER_EN(x) (((x) >>
0) & 0x0F)
+#define C_028B98_STREAM_0_BUFFER_EN
0xFFFFFFF0
+#define S_028B98_STREAM_1_BUFFER_EN(x)
(((unsigned)(x) & 0x0F) << 4)
+#define G_028B98_STREAM_1_BUFFER_EN(x) (((x) >>
4) & 0x0F)
+#define C_028B98_STREAM_1_BUFFER_EN
0xFFFFFF0F
+#define S_028B98_STREAM_2_BUFFER_EN(x)
(((unsigned)(x) & 0x0F) << 8)
+#define G_028B98_STREAM_2_BUFFER_EN(x) (((x) >>
8) & 0x0F)
+#define C_028B98_STREAM_2_BUFFER_EN
0xFFFFF0FF
+#define S_028B98_STREAM_3_BUFFER_EN(x)
(((unsigned)(x) & 0x0F) << 12)
+#define G_028B98_STREAM_3_BUFFER_EN(x) (((x) >>
12) & 0x0F)
+#define C_028B98_STREAM_3_BUFFER_EN
0xFFFF0FFF
+
+#define EG_R_028A4C_PA_SC_MODE_CNTL_1 0x028A4C
+#define EG_S_028A4C_PS_ITER_SAMPLE(x) (((unsigned)(x) & 0x1)
<< 16)
+#define EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((unsigned)(x) & 0x1)
<< 25)
+#define EG_S_028A4C_FORCE_EOV_REZ_ENABLE(x) (((unsigned)(x) & 0x1)
<< 26)
+#define CM_R_028804_DB_EQAA 0x00028804
+#define S_028804_MAX_ANCHOR_SAMPLES(x) (((unsigned)(x) &
0x07) << 0)
+#define G_028804_MAX_ANCHOR_SAMPLES(x) (((x) >> 0) & 0x07)
+#define C_028804_MAX_ANCHOR_SAMPLES 0xFFFFFFF8
+#define S_028804_PS_ITER_SAMPLES(x) (((unsigned)(x) &
0x07) << 4)
+#define G_028804_PS_ITER_SAMPLES(x) (((x) >> 4) & 0x07)
+#define C_028804_PS_ITER_SAMPLES 0xFFFFFF8F
+#define S_028804_MASK_EXPORT_NUM_SAMPLES(x) (((unsigned)(x) &
0x07) << 8)
+#define G_028804_MASK_EXPORT_NUM_SAMPLES(x) (((x) >> 8) & 0x07)
+#define C_028804_MASK_EXPORT_NUM_SAMPLES 0xFFFFF8FF
+#define S_028804_ALPHA_TO_MASK_NUM_SAMPLES(x) (((unsigned)(x) &
0x07) << 12)
+#define G_028804_ALPHA_TO_MASK_NUM_SAMPLES(x) (((x) >> 12) & 0x07)
+#define C_028804_ALPHA_TO_MASK_NUM_SAMPLES 0xFFFF8FFF
+#define S_028804_HIGH_QUALITY_INTERSECTIONS(x) (((unsigned)(x) & 0x1)
<< 16)
+#define G_028804_HIGH_QUALITY_INTERSECTIONS(x) (((x) >> 16) & 0x1)
+#define C_028804_HIGH_QUALITY_INTERSECTIONS 0xFFFEFFFF
+#define S_028804_INCOHERENT_EQAA_READS(x) (((unsigned)(x) & 0x1)
<< 17)
+#define G_028804_INCOHERENT_EQAA_READS(x) (((x) >> 17) & 0x1)
+#define C_028804_INCOHERENT_EQAA_READS 0xFFFDFFFF
+#define S_028804_INTERPOLATE_COMP_Z(x) (((unsigned)(x) & 0x1)
<< 18)
+#define G_028804_INTERPOLATE_COMP_Z(x) (((x) >> 18) & 0x1)
+#define C_028804_INTERPOLATE_COMP_Z 0xFFFBFFFF
+#define S_028804_INTERPOLATE_SRC_Z(x) (((unsigned)(x) & 0x1)
<< 19)
+#define G_028804_INTERPOLATE_SRC_Z(x) (((x) >> 19) & 0x1)
+#define C_028804_INTERPOLATE_SRC_Z 0xFFF7FFFF
+#define S_028804_STATIC_ANCHOR_ASSOCIATIONS(x) (((unsigned)(x) & 0x1)
<< 20)
+#define G_028804_STATIC_ANCHOR_ASSOCIATIONS(x) (((x) >> 20) & 0x1)
+#define C_028804_STATIC_ANCHOR_ASSOCIATIONS 0xFFEFFFFF
+#define S_028804_ALPHA_TO_MASK_EQAA_DISABLE(x) (((unsigned)(x) & 0x1)
<< 21)
+#define G_028804_ALPHA_TO_MASK_EQAA_DISABLE(x) (((x) >> 21) & 0x1)
+#define C_028804_ALPHA_TO_MASK_EQAA_DISABLE 0xFFDFFFFF
+#define S_028804_OVERRASTERIZATION_AMOUNT(x) (((unsigned)(x) &
0x07) << 24)
+#define G_028804_OVERRASTERIZATION_AMOUNT(x) (((x) >> 24) & 0x07)
+#define C_028804_OVERRASTERIZATION_AMOUNT 0xF8FFFFFF
+#define S_028804_ENABLE_POSTZ_OVERRASTERIZATION(x) (((unsigned)(x) & 0x1)
<< 27)
+#define G_028804_ENABLE_POSTZ_OVERRASTERIZATION(x) (((x) >> 27) & 0x1)
+#define C_028804_ENABLE_POSTZ_OVERRASTERIZATION 0xF7FFFFFF
+#define CM_R_028BDC_PA_SC_LINE_CNTL 0x28bdc
+#define S_028BDC_EXPAND_LINE_WIDTH(x) (((unsigned)(x) & 0x1)
<< 9)
+#define G_028BDC_EXPAND_LINE_WIDTH(x) (((x) >> 9) & 0x1)
+#define C_028BDC_EXPAND_LINE_WIDTH 0xFFFFFDFF
+#define S_028BDC_LAST_PIXEL(x) (((unsigned)(x) & 0x1)
<< 10)
+#define G_028BDC_LAST_PIXEL(x) (((x) >> 10) & 0x1)
+#define C_028BDC_LAST_PIXEL 0xFFFFFBFF
+#define S_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((unsigned)(x) & 0x1)
<< 11)
+#define G_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((x) >> 11) & 0x1)
+#define C_028BDC_PERPENDICULAR_ENDCAP_ENA 0xFFFFF7FF
+#define S_028BDC_DX10_DIAMOND_TEST_ENA(x) (((unsigned)(x) & 0x1)
<< 12)
+#define G_028BDC_DX10_DIAMOND_TEST_ENA(x) (((x) >> 12) & 0x1)
+#define C_028BDC_DX10_DIAMOND_TEST_ENA 0xFFFFEFFF
+#define CM_R_028BE0_PA_SC_AA_CONFIG 0x28be0
+#define S_028BE0_MSAA_NUM_SAMPLES(x) (((unsigned)(x) & 0x07)
<< 0)
+#define G_028BE0_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x07)
+#define C_028BE0_MSAA_NUM_SAMPLES 0xFFFFFFF8
+#define S_028BE0_AA_MASK_CENTROID_DTMN(x) (((unsigned)(x) & 0x1)
<< 4)
+#define G_028BE0_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1)
+#define C_028BE0_AA_MASK_CENTROID_DTMN 0xFFFFFFEF
+#define S_028BE0_MAX_SAMPLE_DIST(x) (((unsigned)(x) & 0x0F)
<< 13)
+#define G_028BE0_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0x0F)
+#define C_028BE0_MAX_SAMPLE_DIST 0xFFFE1FFF
+#define S_028BE0_MSAA_EXPOSED_SAMPLES(x) (((unsigned)(x) & 0x07)
<< 20)
+#define G_028BE0_MSAA_EXPOSED_SAMPLES(x) (((x) >> 20) & 0x07)
+#define C_028BE0_MSAA_EXPOSED_SAMPLES 0xFF8FFFFF
+#define S_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((unsigned)(x) & 0x03)
<< 24)
+#define G_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((x) >> 24) & 0x03)
+#define C_028BE0_DETAIL_TO_EXPOSED_MODE 0xFCFFFFFF
+#define CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x28bf8
+#define CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x28c08
+#define CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x28c18
+#define CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x28c28
#define R_008960_VGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x008960 /* read-only */
#define R_008964_VGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x008964 /* read-only */
#define R_008968_VGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x008968 /* read-only */
#define R_00896C_VGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x00896C /* read-only */
#define R_008C00_SQ_CONFIG 0x00008C00
#define S_008C00_VC_ENABLE(x) (((unsigned)(x) & 0x1)
<< 0)
#define G_008C00_VC_ENABLE(x) (((x) >> 0) & 0x1)
#define C_008C00_VC_ENABLE(x) 0xFFFFFFFE
#define S_008C00_EXPORT_SRC_C(x) (((unsigned)(x) & 0x1)
<< 1)
#define G_008C00_EXPORT_SRC_C(x) (((x) >> 1) & 0x1)
diff --git a/src/gallium/drivers/r600/r600_streamout.c
b/src/gallium/drivers/r600/r600_streamout.c
index a18089a..6d45a07 100644
--- a/src/gallium/drivers/r600/r600_streamout.c
+++ b/src/gallium/drivers/r600/r600_streamout.c
@@ -21,20 +21,25 @@
* SOFTWARE.
*
* Authors: Marek Olšák <[email protected]>
*
*/
#include "r600_pipe_common.h"
#include "r600_cs.h"
#include "util/u_memory.h"
+#include "evergreend.h"
+
+#define R_008490_CP_STRMOUT_CNTL 0x008490
+#define R_028AB0_VGT_STRMOUT_EN 0x028AB0
+#define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20
static void r600_set_streamout_enable(struct r600_common_context *rctx, bool
enable);
static struct pipe_stream_output_target *
r600_create_so_target(struct pipe_context *ctx,
struct pipe_resource *buffer,
unsigned buffer_offset,
unsigned buffer_size)
{
struct r600_common_context *rctx = (struct r600_common_context *)ctx;
@@ -150,43 +155,41 @@ void r600_set_streamout_targets(struct pipe_context *ctx,
r600_set_streamout_enable(rctx, false);
}
}
static void r600_flush_vgt_streamout(struct r600_common_context *rctx)
{
struct radeon_winsys_cs *cs = rctx->gfx.cs;
unsigned reg_strmout_cntl;
/* The register is at different places on different ASICs. */
- if (rctx->chip_class >= CIK) {
- reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
- } else if (rctx->chip_class >= EVERGREEN) {
+ if (rctx->chip_class >= EVERGREEN) {
reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
} else {
reg_strmout_cntl = R_008490_CP_STRMOUT_CNTL;
}
if (rctx->chip_class >= CIK) {
radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
} else {
radeon_set_config_reg(cs, reg_strmout_cntl, 0);
}
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) |
EVENT_INDEX(0));
radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is
equal to the reference value */
radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
radeon_emit(cs, 0);
- radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* reference value */
- radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* mask */
+ radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
+ radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
radeon_emit(cs, 4); /* poll interval */
}
static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct
r600_atom *atom)
{
struct radeon_winsys_cs *cs = rctx->gfx.cs;
struct r600_so_target **t = rctx->streamout.targets;
uint16_t *stride_in_dw = rctx->streamout.stride_in_dw;
unsigned i, update_flags = 0;
@@ -319,21 +322,20 @@ static void r600_emit_streamout_enable(struct
r600_common_context *rctx,
unsigned strmout_config_val =
S_028B94_STREAMOUT_0_EN(r600_get_strmout_en(rctx));
unsigned strmout_buffer_reg = R_028B20_VGT_STRMOUT_BUFFER_EN;
unsigned strmout_buffer_val = rctx->streamout.hw_enabled_mask &
rctx->streamout.enabled_stream_buffers_mask;
if (rctx->chip_class >= EVERGREEN) {
strmout_buffer_reg = R_028B98_VGT_STRMOUT_BUFFER_CONFIG;
strmout_config_reg = R_028B94_VGT_STRMOUT_CONFIG;
strmout_config_val |=
- S_028B94_RAST_STREAM(0) |
S_028B94_STREAMOUT_1_EN(r600_get_strmout_en(rctx)) |
S_028B94_STREAMOUT_2_EN(r600_get_strmout_en(rctx)) |
S_028B94_STREAMOUT_3_EN(r600_get_strmout_en(rctx));
}
radeon_set_context_reg(rctx->gfx.cs, strmout_buffer_reg,
strmout_buffer_val);
radeon_set_context_reg(rctx->gfx.cs, strmout_config_reg,
strmout_config_val);
}
static void r600_set_streamout_enable(struct r600_common_context *rctx, bool
enable)
{
diff --git a/src/gallium/drivers/r600/r600_viewport.c
b/src/gallium/drivers/r600/r600_viewport.c
index 2de1382..0797f93 100644
--- a/src/gallium/drivers/r600/r600_viewport.c
+++ b/src/gallium/drivers/r600/r600_viewport.c
@@ -18,20 +18,43 @@
* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include "r600_cs.h"
#include "util/u_viewport.h"
#include "tgsi/tgsi_scan.h"
+#define R600_R_028C0C_PA_CL_GB_VERT_CLIP_ADJ 0x028C0C
+#define CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ 0x28be8
+#define R_02843C_PA_CL_VPORT_XSCALE 0x02843C
+
+#define R_028250_PA_SC_VPORT_SCISSOR_0_TL
0x028250
+#define S_028250_TL_X(x)
(((unsigned)(x) & 0x7FFF) << 0)
+#define G_028250_TL_X(x) (((x) >>
0) & 0x7FFF)
+#define C_028250_TL_X
0xFFFF8000
+#define S_028250_TL_Y(x)
(((unsigned)(x) & 0x7FFF) << 16)
+#define G_028250_TL_Y(x) (((x) >>
16) & 0x7FFF)
+#define C_028250_TL_Y
0x8000FFFF
+#define S_028250_WINDOW_OFFSET_DISABLE(x)
(((unsigned)(x) & 0x1) << 31)
+#define G_028250_WINDOW_OFFSET_DISABLE(x) (((x) >>
31) & 0x1)
+#define C_028250_WINDOW_OFFSET_DISABLE
0x7FFFFFFF
+#define S_028254_BR_X(x)
(((unsigned)(x) & 0x7FFF) << 0)
+#define G_028254_BR_X(x) (((x) >>
0) & 0x7FFF)
+#define C_028254_BR_X
0xFFFF8000
+#define S_028254_BR_Y(x)
(((unsigned)(x) & 0x7FFF) << 16)
+#define G_028254_BR_Y(x) (((x) >>
16) & 0x7FFF)
+#define C_028254_BR_Y
0x8000FFFF
+#define R_0282D0_PA_SC_VPORT_ZMIN_0
0x0282D0
+#define R_0282D4_PA_SC_VPORT_ZMAX_0
0x0282D4
+
#define GET_MAX_SCISSOR(rctx) (rctx->chip_class >= EVERGREEN ? 16384 : 8192)
static void r600_set_scissor_states(struct pipe_context *ctx,
unsigned start_slot,
unsigned num_scissors,
const struct pipe_scissor_state *state)
{
struct r600_common_context *rctx = (struct r600_common_context *)ctx;
int i;
diff --git a/src/gallium/drivers/radeon/r600_cs.h
b/src/gallium/drivers/radeon/r600_cs.h
index b4af5a6..5bfce1c 100644
--- a/src/gallium/drivers/radeon/r600_cs.h
+++ b/src/gallium/drivers/radeon/r600_cs.h
@@ -24,21 +24,21 @@
*/
/**
* This file contains helpers for writing commands to commands streams.
*/
#ifndef R600_CS_H
#define R600_CS_H
#include "r600_pipe_common.h"
-#include "amd/common/r600d_common.h"
+#include "amd/common/sid.h"
/**
* Return true if there is enough memory in VRAM and GTT for the buffers
* added so far.
*
* \param vram VRAM memory size not added to the buffer list yet
* \param gtt GTT memory size not added to the buffer list yet
*/
static inline bool
radeon_cs_memory_below_limit(struct r600_common_screen *screen,
@@ -108,54 +108,54 @@ radeon_add_to_buffer_list_check_mem(struct
r600_common_context *rctx,
!radeon_cs_memory_below_limit(rctx->screen, ring->cs,
rctx->vram + rbo->vram_usage,
rctx->gtt + rbo->gart_usage))
ring->flush(rctx, RADEON_FLUSH_ASYNC, NULL);
return radeon_add_to_buffer_list(rctx, ring, rbo, usage, priority);
}
static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs,
unsigned reg, unsigned num)
{
- assert(reg < R600_CONTEXT_REG_OFFSET);
+ assert(reg < SI_CONTEXT_REG_OFFSET);
assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
- radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2);
+ radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
}
static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned
reg, unsigned value)
{
radeon_set_config_reg_seq(cs, reg, 1);
radeon_emit(cs, value);
}
static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs,
unsigned reg, unsigned num)
{
- assert(reg >= R600_CONTEXT_REG_OFFSET);
+ assert(reg >= SI_CONTEXT_REG_OFFSET);
assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
- radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2);
+ radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
}
static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs,
unsigned reg, unsigned value)
{
radeon_set_context_reg_seq(cs, reg, 1);
radeon_emit(cs, value);
}
static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs,
unsigned reg, unsigned idx,
unsigned value)
{
- assert(reg >= R600_CONTEXT_REG_OFFSET);
+ assert(reg >= SI_CONTEXT_REG_OFFSET);
assert(cs->current.cdw + 3 <= cs->current.max_dw);
radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
- radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
+ radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
radeon_emit(cs, value);
}
static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned
reg, unsigned num)
{
assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
}
diff --git a/src/gallium/drivers/radeon/r600_perfcounter.c
b/src/gallium/drivers/radeon/r600_perfcounter.c
index 13fd1e9..6c68dc4 100644
--- a/src/gallium/drivers/radeon/r600_perfcounter.c
+++ b/src/gallium/drivers/radeon/r600_perfcounter.c
@@ -21,21 +21,21 @@
* SOFTWARE.
*
* Authors:
* Nicolai Hähnle <[email protected]>
*
*/
#include "util/u_memory.h"
#include "r600_query.h"
#include "r600_pipe_common.h"
-#include "amd/common/r600d_common.h"
+#include "amd/common/sid.h"
/* Max counters per HW block */
#define R600_QUERY_MAX_COUNTERS 16
static struct r600_perfcounter_block *
lookup_counter(struct r600_perfcounters *pc, unsigned index,
unsigned *base_gid, unsigned *sub_index)
{
struct r600_perfcounter_block *block = pc->blocks;
unsigned bid;
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index f8a826f..44ff589 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -29,20 +29,21 @@
#include "tgsi/tgsi_parse.h"
#include "util/list.h"
#include "util/u_draw_quad.h"
#include "util/u_memory.h"
#include "util/u_format_s3tc.h"
#include "util/u_upload_mgr.h"
#include "os/os_time.h"
#include "vl/vl_decoder.h"
#include "vl/vl_video_buffer.h"
#include "radeon/radeon_video.h"
+#include "amd/common/sid.h"
#include <inttypes.h>
#include <sys/utsname.h>
#include <llvm-c/TargetMachine.h>
struct r600_multi_fence {
struct pipe_reference reference;
struct pipe_fence_handle *gfx;
struct pipe_fence_handle *sdma;
diff --git a/src/gallium/drivers/radeon/r600_query.c
b/src/gallium/drivers/radeon/r600_query.c
index e4dbb1d..b2809f8 100644
--- a/src/gallium/drivers/radeon/r600_query.c
+++ b/src/gallium/drivers/radeon/r600_query.c
@@ -21,20 +21,21 @@
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include "r600_query.h"
#include "r600_cs.h"
#include "util/u_memory.h"
#include "util/u_upload_mgr.h"
#include "os/os_time.h"
#include "tgsi/tgsi_text.h"
+#include "amd/common/sid.h"
/* TODO: remove this: */
void si_update_prims_generated_query_state(struct r600_common_context *rctx,
unsigned type, int diff);
#define R600_MAX_STREAMS 4
struct r600_hw_query_params {
unsigned start_offset;
unsigned end_offset;
@@ -720,24 +721,24 @@ static void r600_update_occlusion_query_state(struct
r600_common_context *rctx,
rctx->set_occlusion_query_state(&rctx->b, old_enable,
old_perfect_enable);
}
}
}
static unsigned event_type_for_stream(unsigned stream)
{
switch (stream) {
default:
- case 0: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS;
- case 1: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS1;
- case 2: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS2;
- case 3: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS3;
+ case 0: return V_028A90_SAMPLE_STREAMOUTSTATS;
+ case 1: return V_028A90_SAMPLE_STREAMOUTSTATS1;
+ case 2: return V_028A90_SAMPLE_STREAMOUTSTATS2;
+ case 3: return V_028A90_SAMPLE_STREAMOUTSTATS3;
}
}
static void emit_sample_streamout(struct radeon_winsys_cs *cs, uint64_t va,
unsigned stream)
{
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(event_type_for_stream(stream)) |
EVENT_INDEX(3));
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
@@ -748,21 +749,21 @@ static void r600_query_hw_do_emit_start(struct
r600_common_context *ctx,
struct r600_resource *buffer,
uint64_t va)
{
struct radeon_winsys_cs *cs = ctx->gfx.cs;
switch (query->b.type) {
case PIPE_QUERY_OCCLUSION_COUNTER:
case PIPE_QUERY_OCCLUSION_PREDICATE:
case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
- radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) |
EVENT_INDEX(1));
+ radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) |
EVENT_INDEX(1));
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
break;
case PIPE_QUERY_PRIMITIVES_EMITTED:
case PIPE_QUERY_PRIMITIVES_GENERATED:
case PIPE_QUERY_SO_STATISTICS:
case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
emit_sample_streamout(cs, va, query->stream);
break;
case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
@@ -777,21 +778,21 @@ static void r600_query_hw_do_emit_start(struct
r600_common_context *ctx,
radeon_emit(cs, COPY_DATA_COUNT_SEL |
COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
COPY_DATA_DST_SEL(COPY_DATA_MEM_ASYNC));
radeon_emit(cs, 0);
radeon_emit(cs, 0);
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
break;
case PIPE_QUERY_PIPELINE_STATISTICS:
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
- radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) |
EVENT_INDEX(2));
+ radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) |
EVENT_INDEX(2));
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
break;
default:
assert(0);
}
radeon_add_to_buffer_list(ctx, &ctx->gfx, query->buffer.buf,
RADEON_USAGE_WRITE,
RADEON_PRIO_QUERY);
}
@@ -835,21 +836,21 @@ static void r600_query_hw_do_emit_stop(struct
r600_common_context *ctx,
{
struct radeon_winsys_cs *cs = ctx->gfx.cs;
uint64_t fence_va = 0;
switch (query->b.type) {
case PIPE_QUERY_OCCLUSION_COUNTER:
case PIPE_QUERY_OCCLUSION_PREDICATE:
case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
va += 8;
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
- radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) |
EVENT_INDEX(1));
+ radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) |
EVENT_INDEX(1));
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
fence_va = va + ctx->screen->info.num_render_backends * 16 - 8;
break;
case PIPE_QUERY_PRIMITIVES_EMITTED:
case PIPE_QUERY_PRIMITIVES_GENERATED:
case PIPE_QUERY_SO_STATISTICS:
case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
va += 16;
@@ -857,45 +858,45 @@ static void r600_query_hw_do_emit_stop(struct
r600_common_context *ctx,
break;
case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
va += 16;
for (unsigned stream = 0; stream < R600_MAX_STREAMS; ++stream)
emit_sample_streamout(cs, va + 32 * stream, stream);
break;
case PIPE_QUERY_TIME_ELAPSED:
va += 8;
/* fall through */
case PIPE_QUERY_TIMESTAMP:
- si_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
+ si_gfx_write_event_eop(ctx, V_028A90_BOTTOM_OF_PIPE_TS,
0, EOP_DATA_SEL_TIMESTAMP, NULL, va,
0, query->b.type);
fence_va = va + 8;
break;
case PIPE_QUERY_PIPELINE_STATISTICS: {
unsigned sample_size = (query->result_size - 8) / 2;
va += sample_size;
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
- radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) |
EVENT_INDEX(2));
+ radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) |
EVENT_INDEX(2));
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
fence_va = va + sample_size;
break;
}
default:
assert(0);
}
radeon_add_to_buffer_list(ctx, &ctx->gfx, query->buffer.buf,
RADEON_USAGE_WRITE,
RADEON_PRIO_QUERY);
if (fence_va)
- si_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
+ si_gfx_write_event_eop(ctx, V_028A90_BOTTOM_OF_PIPE_TS, 0,
EOP_DATA_SEL_VALUE_32BIT,
query->buffer.buf, fence_va,
0x80000000,
query->b.type);
}
static void r600_query_hw_emit_stop(struct r600_common_context *ctx,
struct r600_query_hw *query)
{
uint64_t va;
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index d9dc10b..78d49c2 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -29,20 +29,21 @@
#include "r600_query.h"
#include "util/u_format.h"
#include "util/u_log.h"
#include "util/u_memory.h"
#include "util/u_pack_color.h"
#include "util/u_surface.h"
#include "os/os_time.h"
#include <errno.h>
#include <inttypes.h>
#include "state_tracker/drm_driver.h"
+#include "amd/common/sid.h"
static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
struct r600_texture *rtex);
static enum radeon_surf_mode
r600_choose_tiling(struct r600_common_screen *rscreen,
const struct pipe_resource *templ);
bool si_prepare_for_dma_blit(struct r600_common_context *rctx,
struct r600_texture *rdst,
@@ -401,21 +402,21 @@ static void r600_texture_discard_cmask(struct
r600_common_screen *rscreen,
if (!rtex->cmask.size)
return;
assert(rtex->resource.b.b.nr_samples <= 1);
/* Disable CMASK. */
memset(&rtex->cmask, 0, sizeof(rtex->cmask));
rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
rtex->dirty_level_mask = 0;
- rtex->cb_color_info &= ~SI_S_028C70_FAST_CLEAR(1);
+ rtex->cb_color_info &= ~S_028C70_FAST_CLEAR(1);
if (rtex->cmask_buffer != &rtex->resource)
r600_resource_reference(&rtex->cmask_buffer, NULL);
/* Notify all contexts about the change. */
p_atomic_inc(&rscreen->dirty_tex_counter);
p_atomic_inc(&rscreen->compressed_colortex_counter);
}
static bool r600_can_disable_dcc(struct r600_texture *rtex)
@@ -842,21 +843,21 @@ static void si_texture_get_cmask_info(struct
r600_common_screen *rscreen,
}
static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
struct r600_texture *rtex)
{
si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment);
rtex->size = rtex->cmask.offset + rtex->cmask.size;
- rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
+ rtex->cb_color_info |= S_028C70_FAST_CLEAR(1);
}
static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen,
struct r600_texture *rtex)
{
if (rtex->cmask_buffer)
return;
assert(rtex->cmask.size == 0);
@@ -869,21 +870,21 @@ static void r600_texture_alloc_cmask_separate(struct
r600_common_screen *rscreen
rtex->cmask.size,
rtex->cmask.alignment);
if (rtex->cmask_buffer == NULL) {
rtex->cmask.size = 0;
return;
}
/* update colorbuffer state bits */
rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
- rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
+ rtex->cb_color_info |= S_028C70_FAST_CLEAR(1);
p_atomic_inc(&rscreen->compressed_colortex_counter);
}
static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
struct r600_texture *rtex)
{
unsigned cl_width, cl_height, width, height;
unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
unsigned num_pipes = rscreen->info.num_tile_pipes;
@@ -2055,67 +2056,67 @@ static void r600_clear_texture(struct pipe_context
*pipe,
pipe_surface_reference(&sf, NULL);
}
unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap)
{
const struct util_format_description *desc =
util_format_description(format);
#define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
- return V_0280A0_SWAP_STD;
+ return V_028C70_SWAP_STD;
if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
return ~0U;
switch (desc->nr_channels) {
case 1:
if (HAS_SWIZZLE(0,X))
- return V_0280A0_SWAP_STD; /* X___ */
+ return V_028C70_SWAP_STD; /* X___ */
else if (HAS_SWIZZLE(3,X))
- return V_0280A0_SWAP_ALT_REV; /* ___X */
+ return V_028C70_SWAP_ALT_REV; /* ___X */
break;
case 2:
if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
(HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
(HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
- return V_0280A0_SWAP_STD; /* XY__ */
+ return V_028C70_SWAP_STD; /* XY__ */
else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
(HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
(HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
/* YX__ */
- return (do_endian_swap ? V_0280A0_SWAP_STD :
V_0280A0_SWAP_STD_REV);
+ return (do_endian_swap ? V_028C70_SWAP_STD :
V_028C70_SWAP_STD_REV);
else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
- return V_0280A0_SWAP_ALT; /* X__Y */
+ return V_028C70_SWAP_ALT; /* X__Y */
else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
- return V_0280A0_SWAP_ALT_REV; /* Y__X */
+ return V_028C70_SWAP_ALT_REV; /* Y__X */
break;
case 3:
if (HAS_SWIZZLE(0,X))
- return (do_endian_swap ? V_0280A0_SWAP_STD_REV :
V_0280A0_SWAP_STD);
+ return (do_endian_swap ? V_028C70_SWAP_STD_REV :
V_028C70_SWAP_STD);
else if (HAS_SWIZZLE(0,Z))
- return V_0280A0_SWAP_STD_REV; /* ZYX */
+ return V_028C70_SWAP_STD_REV; /* ZYX */
break;
case 4:
/* check the middle channels, the 1st and 4th channel can be
NONE */
if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z)) {
- return V_0280A0_SWAP_STD; /* XYZW */
+ return V_028C70_SWAP_STD; /* XYZW */
} else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y)) {
- return V_0280A0_SWAP_STD_REV; /* WZYX */
+ return V_028C70_SWAP_STD_REV; /* WZYX */
} else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X)) {
- return V_0280A0_SWAP_ALT; /* ZYXW */
+ return V_028C70_SWAP_ALT; /* ZYXW */
} else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W)) {
/* YZWX */
if (desc->is_array)
- return V_0280A0_SWAP_ALT_REV;
+ return V_028C70_SWAP_ALT_REV;
else
- return (do_endian_swap ? V_0280A0_SWAP_ALT :
V_0280A0_SWAP_ALT_REV);
+ return (do_endian_swap ? V_028C70_SWAP_ALT :
V_028C70_SWAP_ALT_REV);
}
break;
}
return ~0U;
}
/* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
static void vi_dcc_clean_up_context_slot(struct r600_common_context *rctx,
int slot)
diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c
b/src/gallium/drivers/radeonsi/si_perfcounter.c
index cb3377a..116e0b9 100644
--- a/src/gallium/drivers/radeonsi/si_perfcounter.c
+++ b/src/gallium/drivers/radeonsi/si_perfcounter.c
@@ -595,41 +595,41 @@ static void si_pc_emit_start(struct r600_common_context
*ctx,
radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
COPY_DATA_DST_SEL(COPY_DATA_MEM));
radeon_emit(cs, 1); /* immediate */
radeon_emit(cs, 0); /* unused */
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
S_036020_PERFMON_STATE(V_036020_DISABLE_AND_RESET));
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
- radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PERFCOUNTER_START) |
EVENT_INDEX(0));
+ radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_START) |
EVENT_INDEX(0));
radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
S_036020_PERFMON_STATE(V_036020_START_COUNTING));
}
/* Note: The buffer was already added in si_pc_emit_start, so we don't have to
* do it again in here. */
static void si_pc_emit_stop(struct r600_common_context *ctx,
struct r600_resource *buffer, uint64_t va)
{
struct radeon_winsys_cs *cs = ctx->gfx.cs;
- si_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
+ si_gfx_write_event_eop(ctx, V_028A90_BOTTOM_OF_PIPE_TS, 0,
EOP_DATA_SEL_VALUE_32BIT,
buffer, va, 0, R600_NOT_QUERY);
si_gfx_wait_fence(ctx, va, 0, 0xffffffff);
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
- radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PERFCOUNTER_SAMPLE) |
EVENT_INDEX(0));
+ radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_SAMPLE) |
EVENT_INDEX(0));
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
- radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PERFCOUNTER_STOP) |
EVENT_INDEX(0));
+ radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_STOP) | EVENT_INDEX(0));
radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
S_036020_PERFMON_STATE(V_036020_STOP_COUNTING) |
S_036020_PERFMON_SAMPLE_ENABLE(1));
}
static void si_pc_emit_read(struct r600_common_context *ctx,
struct r600_perfcounter_block *group,
unsigned count, unsigned *selectors,
struct r600_resource *buffer, uint64_t va)
{
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 3c6b7ca..4bfd527 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -202,37 +202,37 @@ static void si_emit_cb_render_state(struct si_context
*sctx, struct r600_atom *a
break;
case V_028C70_COLOR_4_4_4_4:
if (spi_format ==
V_028714_SPI_SHADER_FP16_ABGR) {
sx_ps_downconvert |=
V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
sx_blend_opt_epsilon |=
V_028758_4BIT_FORMAT << (i * 4);
}
break;
case V_028C70_COLOR_32:
- if (swap == V_0280A0_SWAP_STD &&
+ if (swap == V_028C70_SWAP_STD &&
spi_format == V_028714_SPI_SHADER_32_R)
sx_ps_downconvert |=
V_028754_SX_RT_EXPORT_32_R << (i * 4);
- else if (swap == V_0280A0_SWAP_ALT_REV &&
+ else if (swap == V_028C70_SWAP_ALT_REV &&
spi_format ==
V_028714_SPI_SHADER_32_AR)
sx_ps_downconvert |=
V_028754_SX_RT_EXPORT_32_A << (i * 4);
break;
case V_028C70_COLOR_16:
case V_028C70_COLOR_16_16:
/* For 1-channel formats, use the superset
thereof. */
if (spi_format ==
V_028714_SPI_SHADER_UNORM16_ABGR ||
spi_format ==
V_028714_SPI_SHADER_SNORM16_ABGR ||
spi_format ==
V_028714_SPI_SHADER_UINT16_ABGR ||
spi_format ==
V_028714_SPI_SHADER_SINT16_ABGR) {
- if (swap == V_0280A0_SWAP_STD ||
- swap == V_0280A0_SWAP_STD_REV)
+ if (swap == V_028C70_SWAP_STD ||
+ swap == V_028C70_SWAP_STD_REV)
sx_ps_downconvert |=
V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
else
sx_ps_downconvert |=
V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
}
break;
case V_028C70_COLOR_10_11_11:
if (spi_format ==
V_028714_SPI_SHADER_FP16_ABGR) {
sx_ps_downconvert |=
V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
sx_blend_opt_epsilon |=
V_028758_11BIT_FORMAT << (i * 4);
@@ -3321,55 +3321,55 @@ static void si_emit_msaa_config(struct si_context
*sctx, struct r600_atom *atom)
0, /* unused */
4, /* 2x MSAA */
6, /* 4x MSAA */
7, /* 8x MSAA */
8, /* 16x MSAA */
};
unsigned log_samples = util_logbase2(setup_samples);
unsigned log_ps_iter_samples =
util_logbase2(util_next_power_of_two(sctx->ps_iter_samples));
- radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
+ radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
radeon_emit(cs, sc_line_cntl |
S_028BDC_EXPAND_LINE_WIDTH(1)); /*
CM_R_028BDC_PA_SC_LINE_CNTL */
radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /*
CM_R_028BE0_PA_SC_AA_CONFIG */
if (sctx->framebuffer.nr_samples > 1) {
- radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
+ radeon_set_context_reg(cs, R_028804_DB_EQAA,
S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
- radeon_set_context_reg(cs,
EG_R_028A4C_PA_SC_MODE_CNTL_1,
-
EG_S_028A4C_PS_ITER_SAMPLE(sctx->ps_iter_samples > 1) |
+ radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
+
S_028A4C_PS_ITER_SAMPLE(sctx->ps_iter_samples > 1) |
sc_mode_cntl_1);
} else if (sctx->smoothing_enabled) {
- radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
+ radeon_set_context_reg(cs, R_028804_DB_EQAA,
S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
S_028804_OVERRASTERIZATION_AMOUNT(log_samples));
- radeon_set_context_reg(cs,
EG_R_028A4C_PA_SC_MODE_CNTL_1,
+ radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
sc_mode_cntl_1);
}
} else {
- radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
+ radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
radeon_emit(cs, sc_line_cntl); /* CM_R_028BDC_PA_SC_LINE_CNTL */
radeon_emit(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
- radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
+ radeon_set_context_reg(cs, R_028804_DB_EQAA,
S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
- radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
+ radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
sc_mode_cntl_1);
}
/* GFX9: Flush DFSM when the AA mode changes. */
if (sctx->screen->dfsm_allowed) {
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) |
EVENT_INDEX(0));
}
}
diff --git a/src/gallium/drivers/radeonsi/si_state_msaa.c
b/src/gallium/drivers/radeonsi/si_state_msaa.c
index 977f54b..133f1e4 100644
--- a/src/gallium/drivers/radeonsi/si_state_msaa.c
+++ b/src/gallium/drivers/radeonsi/si_state_msaa.c
@@ -127,56 +127,56 @@ static void si_get_sample_position(struct pipe_context
*ctx, unsigned sample_cou
out_value[1] = (float)(val.idx + 8) / 16.0f;
break;
}
}
void si_emit_sample_locations(struct radeon_winsys_cs *cs, int nr_samples)
{
switch (nr_samples) {
default:
case 1:
- radeon_set_context_reg(cs,
CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
- radeon_set_context_reg(cs,
CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
- radeon_set_context_reg(cs,
CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
- radeon_set_context_reg(cs,
CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
+ radeon_set_context_reg(cs,
R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
+ radeon_set_context_reg(cs,
R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
+ radeon_set_context_reg(cs,
R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
+ radeon_set_context_reg(cs,
R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
break;
case 2:
- radeon_set_context_reg(cs,
CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
- radeon_set_context_reg(cs,
CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
- radeon_set_context_reg(cs,
CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
- radeon_set_context_reg(cs,
CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
+ radeon_set_context_reg(cs,
R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
+ radeon_set_context_reg(cs,
R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
+ radeon_set_context_reg(cs,
R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
+ radeon_set_context_reg(cs,
R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
break;
case 4:
- radeon_set_context_reg(cs,
CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
- radeon_set_context_reg(cs,
CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
- radeon_set_context_reg(cs,
CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
- radeon_set_context_reg(cs,
CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
+ radeon_set_context_reg(cs,
R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
+ radeon_set_context_reg(cs,
R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
+ radeon_set_context_reg(cs,
R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
+ radeon_set_context_reg(cs,
R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
break;
case 8:
- radeon_set_context_reg_seq(cs,
CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
+ radeon_set_context_reg_seq(cs,
R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
radeon_emit(cs, sample_locs_8x[0]);
radeon_emit(cs, sample_locs_8x[4]);
radeon_emit(cs, 0);
radeon_emit(cs, 0);
radeon_emit(cs, sample_locs_8x[1]);
radeon_emit(cs, sample_locs_8x[5]);
radeon_emit(cs, 0);
radeon_emit(cs, 0);
radeon_emit(cs, sample_locs_8x[2]);
radeon_emit(cs, sample_locs_8x[6]);
radeon_emit(cs, 0);
radeon_emit(cs, 0);
radeon_emit(cs, sample_locs_8x[3]);
radeon_emit(cs, sample_locs_8x[7]);
break;
case 16:
- radeon_set_context_reg_seq(cs,
CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
+ radeon_set_context_reg_seq(cs,
R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
radeon_emit(cs, sample_locs_16x[0]);
radeon_emit(cs, sample_locs_16x[4]);
radeon_emit(cs, sample_locs_16x[8]);
radeon_emit(cs, sample_locs_16x[12]);
radeon_emit(cs, sample_locs_16x[1]);
radeon_emit(cs, sample_locs_16x[5]);
radeon_emit(cs, sample_locs_16x[9]);
radeon_emit(cs, sample_locs_16x[13]);
radeon_emit(cs, sample_locs_16x[2]);
radeon_emit(cs, sample_locs_16x[6]);
diff --git a/src/gallium/drivers/radeonsi/si_state_streamout.c
b/src/gallium/drivers/radeonsi/si_state_streamout.c
index f4fcf70..9971bc8 100644
--- a/src/gallium/drivers/radeonsi/si_state_streamout.c
+++ b/src/gallium/drivers/radeonsi/si_state_streamout.c
@@ -246,22 +246,22 @@ static void si_flush_vgt_streamout(struct si_context
*sctx)
radeon_set_config_reg(cs, reg_strmout_cntl, 0);
}
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) |
EVENT_INDEX(0));
radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is
equal to the reference value */
radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
radeon_emit(cs, 0);
- radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* reference value */
- radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* mask */
+ radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
+ radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
radeon_emit(cs, 4); /* poll interval */
}
static void si_emit_streamout_begin(struct r600_common_context *rctx, struct
r600_atom *atom)
{
struct si_context *sctx = (struct si_context*)rctx;
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
struct si_streamout_target **t = sctx->streamout.targets;
uint16_t *stride_in_dw = sctx->streamout.stride_in_dw;
unsigned i;
--
2.7.4
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