The IR is reused in different pipeline combinations so we need
to clone it to avoid link time optimistaions messing up the
original copy.
---
src/amd/vulkan/radv_pipeline.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 2a25a423a2..d0e47383d7 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1771,20 +1771,27 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
const VkPipelineShaderStageCreateInfo *stage = pStages[i];
if (!modules[i])
continue;
nir[i] = radv_shader_compile_to_nir(device, modules[i],
stage ? stage->pName :
"main", i,
stage ?
stage->pSpecializationInfo : NULL);
pipeline->active_stages |= mesa_to_vk_shader_stage(i);
+ /* We don't want to alter meta shaders IR directly so clone it
+ * first.
+ */
+ if (nir[i]->info.name) {
+ nir[i] = nir_shader_clone(NULL, nir[i]);
+ }
+
if (first != last) {
nir_variable_mode mask = 0;
if (i != first)
mask = mask | nir_var_shader_in;
if (i != last)
mask = mask | nir_var_shader_out;
nir_lower_io_to_scalar_early(nir[i], mask);
@@ -1880,21 +1887,21 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
code_size);
}
free(gs_copy_code);
}
radv_pipeline_cache_insert_shaders(device, cache, hash,
pipeline->shaders,
(const void**)codes, code_sizes);
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
free(codes[i]);
- if (modules[i] && !modules[i]->nir &&
!pipeline->device->trace_bo)
+ if (modules[i] && !pipeline->device->trace_bo)
ralloc_free(nir[i]);
}
if (fs_m.nir)
ralloc_free(fs_m.nir);
}
static VkResult
radv_pipeline_init(struct radv_pipeline *pipeline,
struct radv_device *device,
--
2.13.6
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