From PIPE_CONTROL command description in gfxspecs:
"Whenever a Binding Table Index (BTI) used by a Render Taget Message
points to a different RENDER_SURFACE_STATE, SW must issue a Render
Target Cache Flush by enabling this bit. When render target flush
is set due to new association of BTI, PS Scoreboard Stall bit must
be set in this packet."
V2: Move the PIPE_CONTROL to update_renderbuffer_surfaces() in
brw_wm_surface_state.c (Ken).
Fixes a fulsim error and a GPU hang described in below JIRA.
JIRA: MD5-322
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 44c87df17d..84c5a81227 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -971,6 +971,20 @@ update_renderbuffer_surfaces(struct brw_context *brw)
emit_null_surface_state(brw, fb, &surf_offsets[rt_start]);
}
+ /* From PIPE_CONTROL command description in gfxspecs:
+
+ "Whenever a Binding Table Index (BTI) used by a Render Taget Message
+ points to a different RENDER_SURFACE_STATE, SW must issue a Render
+ Target Cache Flush by enabling this bit. When render target flush
+ is set due to new association of BTI, PS Scoreboard Stall bit must
+ be set in this packet."
+ */
+ if (devinfo->gen >= 11) {
+ brw_emit_pipe_control_flush(brw,
+ PIPE_CONTROL_RENDER_TARGET_FLUSH |
+ PIPE_CONTROL_STALL_AT_SCOREBOARD);
+ }
+
brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
}
--
2.13.6
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