The VS load input for 16-bit values receives pairs of 16-bit values
packed in 32-bit values. Because of the adjusted format used at:

 anv/pipeline: Use 32-bit surface formats for 16-bit formats

v2: Removed use of stride = 2 on 16-bit sources (Jason Ekstrand)
v3: Fix coding style and typo (Topi Pohjolainen)
    Simplify unshuffle 32-bit to 16-bit using helper function
    (Jason Ekstrand)
v4: Rebase minor changes (Chema Casanova)
---
 src/intel/compiler/brw_fs_nir.cpp | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp
index 27611a21d0..eb45b5df27 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -2450,8 +2450,26 @@ fs_visitor::nir_emit_vs_intrinsic(const fs_builder &bld,
       if (type_sz(dest.type) == 8)
          first_component /= 2;
 
-      for (unsigned j = 0; j < num_components; j++) {
-         bld.MOV(offset(dest, bld, j), offset(src, bld, j + first_component));
+      if (type_sz(dest.type) == 2) {
+         /* The VS load input for 16-bit values receives pairs of 16-bit
+          * values packed in 32-bit values. This is an example on SIMD8:
+          *
+          * xy xy xy xy xy xy xy xy
+          * zw zw zw zw zw zw zw xw
+          *
+          * We need to format it to something like:
+          *
+          * xx xx xx xx yy yy yy yy
+          * zz zz zz zz ww ww ww ww
+          */
+
+         shuffle_32bit_load_result_to_16bit_data(bld,
+                                                 dest,
+                                                 retype(src, 
BRW_REGISTER_TYPE_F),
+                                                 num_components);
+      } else {
+         for (unsigned j = 0; j < num_components; j++)
+            bld.MOV(offset(dest, bld, j), offset(src, bld, j + 
first_component));
       }
 
       if (type_sz(dest.type) == 8) {
-- 
2.14.3

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