From intel Skylake PRM, vol 07, section "EU Overview", subsection
"Send Message" (page 905):

   "Bit 30: Data format. This field specifies the width of data read
            from sampler or written to render target. Format = U1 0
            Single Precision (32b), 1 Half Precision (16b)"

Also present on vol 02d, "Message Descriptor - Render Target Write"
(page 326).

It is worth to note that this bit is also present on
Cherryview/Braswell but not on Broadwell, both Gen8, so we can't check
for the presence of that bit based just on the gen (example: on
brw_inst.h).

Signed-off-by: Jose Maria Casanova Crespo <jmcasan...@igalia.com>
Signed-off-by: Eduardo Lima <el...@igalia.com>
Signed-off-by: Alejandro PiƱeiro <apinhe...@igalia.com>
---
 src/intel/compiler/brw_eu.h                   |  6 ++++--
 src/intel/compiler/brw_eu_emit.c              | 25 ++++++++++++++++++++-----
 src/intel/compiler/brw_fs.cpp                 |  1 +
 src/intel/compiler/brw_fs_generator.cpp       |  3 ++-
 src/intel/compiler/brw_fs_surface_builder.cpp |  3 ++-
 src/intel/compiler/brw_inst.h                 |  1 +
 src/intel/compiler/brw_shader.h               |  7 +++++++
 src/intel/compiler/brw_vec4_generator.cpp     |  3 ++-
 8 files changed, 39 insertions(+), 10 deletions(-)

diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 2d0f56f793..35adb47684 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -251,7 +251,8 @@ void brw_set_dp_write_message(struct brw_codegen *p,
                              unsigned last_render_target,
                              unsigned response_length,
                              unsigned end_of_thread,
-                             unsigned send_commit_msg);
+                             unsigned send_commit_msg,
+                             unsigned data_format);
 
 void brw_urb_WRITE(struct brw_codegen *p,
                   struct brw_reg dest,
@@ -303,7 +304,8 @@ void brw_fb_WRITE(struct brw_codegen *p,
                   unsigned response_length,
                   bool eot,
                   bool last_render_target,
-                  bool header_present);
+                  bool header_present,
+                  unsigned data_format);
 
 brw_inst *gen9_fb_READ(struct brw_codegen *p,
                        struct brw_reg dst,
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index c25d8d6eda..456ff32712 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -520,7 +520,8 @@ brw_set_dp_write_message(struct brw_codegen *p,
                         unsigned last_render_target,
                         unsigned response_length,
                         unsigned end_of_thread,
-                        unsigned send_commit_msg)
+                        unsigned send_commit_msg,
+                        unsigned data_format)
 {
    const struct gen_device_info *devinfo = p->devinfo;
    const unsigned sfid = (devinfo->gen >= 6 ? target_cache :
@@ -532,6 +533,16 @@ brw_set_dp_write_message(struct brw_codegen *p,
    brw_inst_set_binding_table_index(devinfo, insn, binding_table_index);
    brw_inst_set_dp_write_msg_type(devinfo, insn, msg_type);
    brw_inst_set_dp_write_msg_control(devinfo, insn, msg_control);
+   if (data_format) {
+      /* data_format is supported since CherryView. So we can't just set the
+       * any data_format value, because it would trigger an assertion on
+       * brw_inst_set_data_format for previous hw if they try to set it to
+       * zero. And we don't add an generation assert because as mentioned,
+       * brw_inst_set_data_format already does that.
+       */
+      brw_inst_set_data_format(devinfo, insn, data_format);
+   }
+
    brw_inst_set_rt_last(devinfo, insn, last_render_target);
    if (devinfo->gen < 7) {
       brw_inst_set_dp_write_commit(devinfo, insn, send_commit_msg);
@@ -2063,7 +2074,8 @@ void brw_oword_block_write_scratch(struct brw_codegen *p,
                               0, /* not a render target */
                               send_commit_msg, /* response_length */
                               0, /* eot */
-                              send_commit_msg);
+                              send_commit_msg,
+                              0 /* data_format */);
    }
 }
 
@@ -2257,7 +2269,8 @@ void brw_fb_WRITE(struct brw_codegen *p,
                   unsigned response_length,
                   bool eot,
                   bool last_render_target,
-                  bool header_present)
+                  bool header_present,
+                  unsigned data_format)
 {
    const struct gen_device_info *devinfo = p->devinfo;
    const unsigned target_cache =
@@ -2305,7 +2318,8 @@ void brw_fb_WRITE(struct brw_codegen *p,
                            last_render_target,
                            response_length,
                            eot,
-                           0 /* send_commit_msg */);
+                           0, /* send_commit_msg */
+                           data_format);
 }
 
 brw_inst *
@@ -2818,7 +2832,8 @@ brw_svb_write(struct brw_codegen *p,
                             0, /* last_render_target: ignored */
                             send_commit_msg, /* response_length */
                             0, /* end_of_thread */
-                            send_commit_msg); /* send_commit_msg */
+                            send_commit_msg, /* send_commit_msg */
+                            0 /* data_format */);
 }
 
 static unsigned
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index bed632d21b..449588c484 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -60,6 +60,7 @@ fs_inst::init(enum opcode opcode, uint8_t exec_size, const 
fs_reg &dst,
    this->sources = sources;
    this->exec_size = exec_size;
    this->base_mrf = -1;
+   this->data_format = 0;
 
    assert(dst.file != IMM && dst.file != UNIFORM);
 
diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index cd5be054f6..247b2b9689 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -302,7 +302,8 @@ fs_generator::fire_fb_write(fs_inst *inst,
                 0,
                 inst->eot,
                 last_render_target,
-                inst->header_size != 0);
+                inst->header_size != 0,
+                inst->data_format);
 
    brw_mark_surface_used(&prog_data->base, surf_index);
 }
diff --git a/src/intel/compiler/brw_fs_surface_builder.cpp 
b/src/intel/compiler/brw_fs_surface_builder.cpp
index c346ef9e70..e0ea3d9dce 100644
--- a/src/intel/compiler/brw_fs_surface_builder.cpp
+++ b/src/intel/compiler/brw_fs_surface_builder.cpp
@@ -38,7 +38,7 @@ namespace brw {
          emit_send(const fs_builder &bld, enum opcode opcode,
                    const fs_reg &addr, const fs_reg &src, const fs_reg 
&surface,
                    unsigned dims, unsigned arg, unsigned rsize,
-                   brw_predicate pred = BRW_PREDICATE_NONE)
+                   brw_predicate pred = BRW_PREDICATE_NONE, unsigned 
data_format = 0)
          {
             /* Reduce the dynamically uniform surface index to a single
              * scalar.
@@ -50,6 +50,7 @@ namespace brw {
             const fs_reg dst = bld.vgrf(BRW_REGISTER_TYPE_UD, rsize);
             fs_inst *inst = bld.emit(opcode, dst, srcs, ARRAY_SIZE(srcs));
 
+            inst->data_format = data_format;
             inst->size_written = rsize * dst.component_size(inst->exec_size);
             inst->predicate = pred;
             return dst;
diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h
index 99e637e660..2501d6adff 100644
--- a/src/intel/compiler/brw_inst.h
+++ b/src/intel/compiler/brw_inst.h
@@ -463,6 +463,7 @@ FC(gen4_pop_count,  115, 112, devinfo->gen < 6)
  *  @{
  */
 F(eot,                 127, 127)
+FC(data_format,        126,  126, devinfo->gen >= 9 || devinfo->is_cherryview)
 FF(mlen,
    /* 4:   */ 119, 116,
    /* 4.5: */ 119, 116,
diff --git a/src/intel/compiler/brw_shader.h b/src/intel/compiler/brw_shader.h
index 06abdc4d17..8f56e0328c 100644
--- a/src/intel/compiler/brw_shader.h
+++ b/src/intel/compiler/brw_shader.h
@@ -153,6 +153,13 @@ struct backend_instruction {
 
    uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
    uint8_t mlen; /**< SEND message length */
+
+   /* Half Precision Data Format for 16-bit payload SEND messages
+    *  0 = 32-bit
+    *  1 = 16-bit
+    */
+   unsigned data_format:1;
+
    int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
    uint8_t target; /**< MRT target. */
    unsigned size_written; /**< Data written to the destination register in 
bytes. */
diff --git a/src/intel/compiler/brw_vec4_generator.cpp 
b/src/intel/compiler/brw_vec4_generator.cpp
index f5d6ad8e48..5901aa43a4 100644
--- a/src/intel/compiler/brw_vec4_generator.cpp
+++ b/src/intel/compiler/brw_vec4_generator.cpp
@@ -1254,7 +1254,8 @@ generate_scratch_write(struct brw_codegen *p,
                            false, /* not a render target write */
                            write_commit, /* rlen */
                            false, /* eot */
-                           write_commit);
+                           write_commit,
+                           0 /* data_format */ );
 }
 
 static void
-- 
2.14.3

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