Use L3 configuration table specified in h/w specification.
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
Cc: Kenneth Graunke <kenn...@whitecape.org>
Cc: Francisco Jerez <curroje...@riseup.net>
Cc: Lionel Landwerlin <lionel.g.landwer...@intel.com>
---
src/intel/common/gen_l3_config.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
index b977c6ab136..079608198bc 100644
--- a/src/intel/common/gen_l3_config.c
+++ b/src/intel/common/gen_l3_config.c
@@ -137,12 +137,16 @@ static const struct gen_l3_config cnl_l3_configs[] = {
*/
static const struct gen_l3_config icl_l3_configs[] = {
/* SLM URB ALL DC RO IS C T */
- {{ 0, 64, 64, 0, 0, 0, 0, 0 }},
- {{ 0, 64, 0, 16, 48, 0, 0, 0 }},
- {{ 0, 48, 0, 16, 64, 0, 0, 0 }},
- {{ 0, 32, 0, 0, 96, 0, 0, 0 }},
- {{ 0, 32, 96, 0, 0, 0, 0, 0 }},
- {{ 0, 32, 0, 16, 80, 0, 0, 0 }},
+ {{ 0, 32, 32, 0, 0, 0, 0, 0 }},
+ {{ 0, 32, 28, 0, 0, 0, 0, 0 }},
+ {{ 0, 24, 0, 8, 28, 0, 0, 0 }},
+ {{ 0, 16, 0, 0, 44, 0, 0, 0 }},
+ {{ 0, 16, 12, 0, 0, 0, 0, 0 }},
+ {{ 0, 16, 0, 0, 12, 0, 0, 0 }},
+ {{ 0, 16, 80, 0, 0, 0, 0, 0 }},
+ {{ 0, 16, 48, 0, 0, 0, 0, 0 }},
+ {{ 0, 16, 44, 0, 0, 0, 0, 0 }},
+ {{ 0, 32, 64, 0, 0, 0, 0, 0 }},
{{ 0 }}
};
--
2.17.1
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