On Mon, Nov 26, 2018 at 11:47 AM Francisco Jerez <curroje...@riseup.net> wrote:
>
> Anuj Phogat <anuj.pho...@gmail.com> writes:
>
> > L3 allocation table in h/w specification recommends using 4 KB
> > granularity for programming allocation fields in L3CNTLREG.
> >
> > Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
> > Cc: Kenneth Graunke <kenn...@whitecape.org>
> > Cc: Francisco Jerez <curroje...@riseup.net>
> > Cc: Lionel Landwerlin <lionel.g.landwer...@intel.com>
> > ---
> > src/mesa/drivers/dri/i965/brw_defines.h | 1 +
> > src/mesa/drivers/dri/i965/gen7_l3_state.c | 1 +
> > 2 files changed, 2 insertions(+)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
> > b/src/mesa/drivers/dri/i965/brw_defines.h
> > index 897c91aa31e..b8ada02d6eb 100644
> > --- a/src/mesa/drivers/dri/i965/brw_defines.h
> > +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> > @@ -1647,6 +1647,7 @@ enum brw_pixel_shader_coverage_mask_mode {
> > # define GEN8_L3CNTLREG_ALL_ALLOC_SHIFT 25
> > # define GEN8_L3CNTLREG_ALL_ALLOC_MASK INTEL_MASK(31, 25)
> > # define GEN8_L3CNTLREG_EDBC_NO_HANG (1 << 9)
> > +# define GEN8_L3CNTLREG_USE_FULL_WAYS (1 << 10)
> >
>
> This bit only exists in Gen11, you should probably prefix the define
> with GEN11 instead. With that fixed:
Fixed locally. Thanks.
>
> Reviewed-by: Francisco Jerez <curroje...@riseup.net>
>
> > #define GEN10_CACHE_MODE_SS 0x0e420
> > #define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
> > diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c
> > b/src/mesa/drivers/dri/i965/gen7_l3_state.c
> > index 8c6c4c47481..fb9b2703a50 100644
> > --- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
> > +++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
> > @@ -119,6 +119,7 @@ setup_l3_config(struct brw_context *brw, const struct
> > gen_l3_config *cfg)
> > assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] &&
> > !cfg->n[GEN_L3P_T]);
> >
> > const unsigned imm_data = ((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0)
> > |
> > + (devinfo->gen == 11 ? GEN8_L3CNTLREG_USE_FULL_WAYS : 0) |
> > SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
> > SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
> > SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
> > --
> > 2.17.1
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