[Mesa-dev] [PATCH 3/8] radeonsi: don't use WRITE_DATA.DST_SEL == MEM_GRBM on >= CIK

[Marek Olšák]

From: Marek Olšák <marek.ol...@amd.com>

---
 src/gallium/drivers/radeonsi/si_pipe.c       | 3 ++-
 src/gallium/drivers/radeonsi/si_state_draw.c | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index b2eb91dca92..f68ef3f67ce 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -525,21 +525,22 @@ static struct pipe_context *si_create_context(struct 
pipe_screen *screen,
 
        if (sctx->chip_class >= GFX9) {
                sctx->wait_mem_scratch = r600_resource(
                        pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4));
                if (!sctx->wait_mem_scratch)
                        goto fail;
 
                /* Initialize the memory. */
                struct radeon_cmdbuf *cs = sctx->gfx_cs;
                radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
-               radeon_emit(cs, S_370_DST_SEL(V_370_MEM_GRBM) |
+               radeon_emit(cs, S_370_DST_SEL(sctx->chip_class >= CIK ? 
V_370_MEM
+                                                                     : 
V_370_MEM_GRBM) |
                            S_370_WR_CONFIRM(1) |
                            S_370_ENGINE_SEL(V_370_ME));
                radeon_emit(cs, sctx->wait_mem_scratch->gpu_address);
                radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32);
                radeon_emit(cs, sctx->wait_mem_number);
                radeon_add_to_buffer_list(sctx, cs, sctx->wait_mem_scratch,
                                          RADEON_USAGE_WRITE, 
RADEON_PRIO_FENCE);
        }
 
        /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c 
b/src/gallium/drivers/radeonsi/si_state_draw.c
index ea8c5d054b5..9a80bd81327 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1589,21 +1589,22 @@ si_draw_rectangle(struct blitter_context *blitter,
        si_draw_vbo(pipe, &info);
 }
 
 void si_trace_emit(struct si_context *sctx)
 {
        struct radeon_cmdbuf *cs = sctx->gfx_cs;
        uint64_t va = sctx->current_saved_cs->trace_buf->gpu_address;
        uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
 
        radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
-       radeon_emit(cs, S_370_DST_SEL(V_370_MEM_GRBM) |
+       radeon_emit(cs, S_370_DST_SEL(sctx->chip_class >= CIK ? V_370_MEM
+                                                             : V_370_MEM_GRBM) 
|
                    S_370_WR_CONFIRM(1) |
                    S_370_ENGINE_SEL(V_370_ME));
        radeon_emit(cs, va);
        radeon_emit(cs, va >> 32);
        radeon_emit(cs, trace_id);
        radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
        radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
 
        if (sctx->log)
                u_log_flush(sctx->log);
-- 
2.17.1

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