FYI, I'm squashing this patch into patch 8.
Marek
On Fri, Jan 18, 2019 at 8:23 PM Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
wrote:
> Ack, patches 1-6 are
>
> Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
>
> On Sat, Jan 19, 2019 at 2:08 AM Marek Olšák <mar...@gmail.com> wrote:
> >
> > On Fri, Jan 18, 2019 at 6:05 PM Bas Nieuwenhuizen <
> b...@basnieuwenhuizen.nl> wrote:
> >>
> >> On Fri, Jan 18, 2019 at 5:44 PM Marek Olšák <mar...@gmail.com> wrote:
> >> >
> >> > From: Marek Olšák <marek.ol...@amd.com>
> >> >
> >> > ---
> >> > src/gallium/drivers/radeonsi/si_buffer.c | 27
> ++++++++++++++++++++++++
> >> > src/gallium/drivers/radeonsi/si_pipe.h | 1 +
> >> > 2 files changed, 28 insertions(+)
> >> >
> >> > diff --git a/src/gallium/drivers/radeonsi/si_buffer.c
> b/src/gallium/drivers/radeonsi/si_buffer.c
> >> > index 4766cf4bdfa..a1e421b8b0d 100644
> >> > --- a/src/gallium/drivers/radeonsi/si_buffer.c
> >> > +++ b/src/gallium/drivers/radeonsi/si_buffer.c
> >> > @@ -16,20 +16,22 @@
> >> > * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> >> > * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> >> > * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO
> EVENT SHALL
> >> > * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
> >> > * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
> TORT OR
> >> > * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
> SOFTWARE OR THE
> >> > * USE OR OTHER DEALINGS IN THE SOFTWARE.
> >> > */
> >> >
> >> > #include "radeonsi/si_pipe.h"
> >> > +#include "sid.h"
> >> > +
> >> > #include "util/u_memory.h"
> >> > #include "util/u_upload_mgr.h"
> >> > #include "util/u_transfer.h"
> >> > #include <inttypes.h>
> >> > #include <stdio.h>
> >> >
> >> > bool si_rings_is_buffer_referenced(struct si_context *sctx,
> >> > struct pb_buffer *buf,
> >> > enum radeon_bo_usage usage)
> >> > {
> >> > @@ -506,20 +508,38 @@ static void *si_buffer_transfer_map(struct
> pipe_context *ctx,
> >> > data = si_buffer_map_sync_with_rings(sctx, rbuffer, usage);
> >> > if (!data) {
> >> > return NULL;
> >> > }
> >> > data += box->x;
> >> >
> >> > return si_buffer_get_transfer(ctx, resource, usage, box,
> >> > ptransfer, data, NULL, 0);
> >> > }
> >> >
> >> > +static void si_buffer_write_data(struct si_context *sctx, struct
> r600_resource *buf,
> >> > + unsigned offset, unsigned size,
> const void *data)
> >> > +{
> >> > + struct radeon_cmdbuf *cs = sctx->gfx_cs;
> >> > +
> >> > + si_need_gfx_cs_space(sctx);
> >> > +
> >> > + sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
> >> > + SI_CONTEXT_CS_PARTIAL_FLUSH |
> >> > + si_get_flush_flags(sctx, SI_COHERENCY_SHADER,
> L2_LRU);
> >> > + si_emit_cache_flush(sctx);
> >>
> >> Maybe only do the cache flush if the buffer is referenced by the
> >> current cmd buffer?
> >
> >
> > We can't do that, because 2 consecutive IBs can execute simultaneously
> for a moment.
> >
> > Marek
>
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