From: Marek Olšák <[email protected]>
---
src/gallium/drivers/radeonsi/si_buffer.c | 138 +++++++++---------
src/gallium/drivers/radeonsi/si_descriptors.c | 48 +++---
src/gallium/drivers/radeonsi/si_pipe.h | 14 +-
src/gallium/drivers/radeonsi/si_state.h | 2 +-
.../drivers/radeonsi/si_state_streamout.c | 4 +-
5 files changed, 103 insertions(+), 103 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_buffer.c
b/src/gallium/drivers/radeonsi/si_buffer.c
index 5c93eacc4b1..200aaa32ebb 100644
--- a/src/gallium/drivers/radeonsi/si_buffer.c
+++ b/src/gallium/drivers/radeonsi/si_buffer.c
@@ -243,62 +243,62 @@ bool si_alloc_resource(struct si_screen *sscreen,
fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Buffer
%"PRIu64" bytes\n",
res->gpu_address, res->gpu_address + res->buf->size,
res->buf->size);
}
return true;
}
static void si_buffer_destroy(struct pipe_screen *screen,
struct pipe_resource *buf)
{
- struct si_resource *rbuffer = si_resource(buf);
+ struct si_resource *buffer = si_resource(buf);
threaded_resource_deinit(buf);
- util_range_destroy(&rbuffer->valid_buffer_range);
- pb_reference(&rbuffer->buf, NULL);
- FREE(rbuffer);
+ util_range_destroy(&buffer->valid_buffer_range);
+ pb_reference(&buffer->buf, NULL);
+ FREE(buffer);
}
/* Reallocate the buffer a update all resource bindings where the buffer is
* bound.
*
* This is used to avoid CPU-GPU synchronizations, because it makes the buffer
* idle by discarding its contents.
*/
static bool
si_invalidate_buffer(struct si_context *sctx,
- struct si_resource *rbuffer)
+ struct si_resource *buf)
{
/* Shared buffers can't be reallocated. */
- if (rbuffer->b.is_shared)
+ if (buf->b.is_shared)
return false;
/* Sparse buffers can't be reallocated. */
- if (rbuffer->flags & RADEON_FLAG_SPARSE)
+ if (buf->flags & RADEON_FLAG_SPARSE)
return false;
/* In AMD_pinned_memory, the user pointer association only gets
* broken when the buffer is explicitly re-allocated.
*/
- if (rbuffer->b.is_user_ptr)
+ if (buf->b.is_user_ptr)
return false;
/* Check if mapping this buffer would cause waiting for the GPU. */
- if (si_rings_is_buffer_referenced(sctx, rbuffer->buf,
RADEON_USAGE_READWRITE) ||
- !sctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
- uint64_t old_va = rbuffer->gpu_address;
+ if (si_rings_is_buffer_referenced(sctx, buf->buf,
RADEON_USAGE_READWRITE) ||
+ !sctx->ws->buffer_wait(buf->buf, 0, RADEON_USAGE_READWRITE)) {
+ uint64_t old_va = buf->gpu_address;
/* Reallocate the buffer in the same pipe_resource. */
- si_alloc_resource(sctx->screen, rbuffer);
- si_rebind_buffer(sctx, &rbuffer->b.b, old_va);
+ si_alloc_resource(sctx->screen, buf);
+ si_rebind_buffer(sctx, &buf->b.b, old_va);
} else {
- util_range_set_empty(&rbuffer->valid_buffer_range);
+ util_range_set_empty(&buf->valid_buffer_range);
}
return true;
}
/* Replace the storage of dst with src. */
void si_replace_buffer_storage(struct pipe_context *ctx,
struct pipe_resource *dst,
struct pipe_resource *src)
{
@@ -320,25 +320,25 @@ void si_replace_buffer_storage(struct pipe_context *ctx,
assert(sdst->bo_alignment == ssrc->bo_alignment);
assert(sdst->domains == ssrc->domains);
si_rebind_buffer(sctx, dst, old_gpu_address);
}
static void si_invalidate_resource(struct pipe_context *ctx,
struct pipe_resource *resource)
{
struct si_context *sctx = (struct si_context*)ctx;
- struct si_resource *rbuffer = si_resource(resource);
+ struct si_resource *buf = si_resource(resource);
/* We currently only do anyting here for buffers */
if (resource->target == PIPE_BUFFER)
- (void)si_invalidate_buffer(sctx, rbuffer);
+ (void)si_invalidate_buffer(sctx, buf);
}
static void *si_buffer_get_transfer(struct pipe_context *ctx,
struct pipe_resource *resource,
unsigned usage,
const struct pipe_box *box,
struct pipe_transfer **ptransfer,
void *data, struct si_resource *staging,
unsigned offset)
{
@@ -365,98 +365,98 @@ static void *si_buffer_get_transfer(struct pipe_context
*ctx,
}
static void *si_buffer_transfer_map(struct pipe_context *ctx,
struct pipe_resource *resource,
unsigned level,
unsigned usage,
const struct pipe_box *box,
struct pipe_transfer **ptransfer)
{
struct si_context *sctx = (struct si_context*)ctx;
- struct si_resource *rbuffer = si_resource(resource);
+ struct si_resource *buf = si_resource(resource);
uint8_t *data;
assert(box->x + box->width <= resource->width0);
/* From GL_AMD_pinned_memory issues:
*
* 4) Is glMapBuffer on a shared buffer guaranteed to return the
* same system address which was specified at creation time?
*
* RESOLVED: NO. The GL implementation might return a different
* virtual mapping of that memory, although the same physical
* page will be used.
*
* So don't ever use staging buffers.
*/
- if (rbuffer->b.is_user_ptr)
+ if (buf->b.is_user_ptr)
usage |= PIPE_TRANSFER_PERSISTENT;
/* See if the buffer range being mapped has never been initialized,
* in which case it can be mapped unsynchronized. */
if (!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED)) &&
usage & PIPE_TRANSFER_WRITE &&
- !rbuffer->b.is_shared &&
- !util_ranges_intersect(&rbuffer->valid_buffer_range, box->x, box->x
+ box->width)) {
+ !buf->b.is_shared &&
+ !util_ranges_intersect(&buf->valid_buffer_range, box->x, box->x +
box->width)) {
usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
}
/* If discarding the entire range, discard the whole resource instead.
*/
if (usage & PIPE_TRANSFER_DISCARD_RANGE &&
box->x == 0 && box->width == resource->width0) {
usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
}
/* If a buffer in VRAM is too large and the range is discarded, don't
* map it directly. This makes sure that the buffer stays in VRAM.
*/
bool force_discard_range = false;
if (usage & (PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE |
PIPE_TRANSFER_DISCARD_RANGE) &&
!(usage & PIPE_TRANSFER_PERSISTENT) &&
/* Try not to decrement the counter if it's not positive. Still
racy,
* but it makes it harder to wrap the counter from INT_MIN to
INT_MAX. */
- rbuffer->max_forced_staging_uploads > 0 &&
- p_atomic_dec_return(&rbuffer->max_forced_staging_uploads) >= 0) {
+ buf->max_forced_staging_uploads > 0 &&
+ p_atomic_dec_return(&buf->max_forced_staging_uploads) >= 0) {
usage &= ~(PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE |
PIPE_TRANSFER_UNSYNCHRONIZED);
usage |= PIPE_TRANSFER_DISCARD_RANGE;
force_discard_range = true;
}
if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE &&
!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
TC_TRANSFER_MAP_NO_INVALIDATE))) {
assert(usage & PIPE_TRANSFER_WRITE);
- if (si_invalidate_buffer(sctx, rbuffer)) {
+ if (si_invalidate_buffer(sctx, buf)) {
/* At this point, the buffer is always idle. */
usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
} else {
/* Fall back to a temporary buffer. */
usage |= PIPE_TRANSFER_DISCARD_RANGE;
}
}
if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
((!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
PIPE_TRANSFER_PERSISTENT))) ||
- (rbuffer->flags & RADEON_FLAG_SPARSE))) {
+ (buf->flags & RADEON_FLAG_SPARSE))) {
assert(usage & PIPE_TRANSFER_WRITE);
/* Check if mapping this buffer would cause waiting for the GPU.
*/
- if (rbuffer->flags & RADEON_FLAG_SPARSE ||
+ if (buf->flags & RADEON_FLAG_SPARSE ||
force_discard_range ||
- si_rings_is_buffer_referenced(sctx, rbuffer->buf,
RADEON_USAGE_READWRITE) ||
- !sctx->ws->buffer_wait(rbuffer->buf, 0,
RADEON_USAGE_READWRITE)) {
+ si_rings_is_buffer_referenced(sctx, buf->buf,
RADEON_USAGE_READWRITE) ||
+ !sctx->ws->buffer_wait(buf->buf, 0,
RADEON_USAGE_READWRITE)) {
unsigned alloc_start = box->x % SI_MAP_BUFFER_ALIGNMENT;
unsigned alloc_size = alloc_start + box->width;
/* Use PKT3_WRITE_DATA for small uploads. */
if (box->width <= SI_TRANSFER_WRITE_DATA_THRESHOLD &&
box->x % 4 == 0 && box->width % 4 == 0) {
void *cpu_map =
u_cpu_suballoc(&sctx->cpu_suballoc, alloc_size,
SI_MAP_BUFFER_ALIGNMENT);
cpu_map = (char*)cpu_map + alloc_start;
@@ -472,34 +472,34 @@ static void *si_buffer_transfer_map(struct pipe_context
*ctx,
u_upload_alloc(ctx->stream_uploader, 0,
alloc_size,
sctx->screen->info.tcc_cache_line_size,
&offset, (struct
pipe_resource**)&staging,
(void**)&data);
if (staging) {
data += alloc_start;
return si_buffer_get_transfer(ctx, resource,
usage, box,
ptransfer,
data, staging, offset);
- } else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
+ } else if (buf->flags & RADEON_FLAG_SPARSE) {
return NULL;
}
} else {
/* At this point, the buffer is always idle (we checked
it above). */
usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
}
}
/* Use a staging buffer in cached GTT for reads. */
else if (((usage & PIPE_TRANSFER_READ) &&
!(usage & PIPE_TRANSFER_PERSISTENT) &&
- (rbuffer->domains & RADEON_DOMAIN_VRAM ||
- rbuffer->flags & RADEON_FLAG_GTT_WC)) ||
- (rbuffer->flags & RADEON_FLAG_SPARSE)) {
+ (buf->domains & RADEON_DOMAIN_VRAM ||
+ buf->flags & RADEON_FLAG_GTT_WC)) ||
+ (buf->flags & RADEON_FLAG_SPARSE)) {
struct si_resource *staging;
assert(!(usage & TC_TRANSFER_MAP_THREADED_UNSYNC));
staging = si_resource(pipe_buffer_create(
ctx->screen, 0, PIPE_USAGE_STAGING,
box->width + (box->x %
SI_MAP_BUFFER_ALIGNMENT)));
if (staging) {
/* Copy the VRAM buffer to the staging buffer. */
sctx->dma_copy(ctx, &staging->b.b, 0,
box->x % SI_MAP_BUFFER_ALIGNMENT,
@@ -508,26 +508,26 @@ static void *si_buffer_transfer_map(struct pipe_context
*ctx,
data = si_buffer_map_sync_with_rings(sctx, staging,
usage &
~PIPE_TRANSFER_UNSYNCHRONIZED);
if (!data) {
si_resource_reference(&staging, NULL);
return NULL;
}
data += box->x % SI_MAP_BUFFER_ALIGNMENT;
return si_buffer_get_transfer(ctx, resource, usage, box,
ptransfer, data,
staging, 0);
- } else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
+ } else if (buf->flags & RADEON_FLAG_SPARSE) {
return NULL;
}
}
- data = si_buffer_map_sync_with_rings(sctx, rbuffer, usage);
+ data = si_buffer_map_sync_with_rings(sctx, buf, usage);
if (!data) {
return NULL;
}
data += box->x;
return si_buffer_get_transfer(ctx, resource, usage, box,
ptransfer, data, NULL, 0);
}
static void si_buffer_write_data(struct si_context *sctx, struct si_resource
*buf,
@@ -547,34 +547,34 @@ static void si_buffer_write_data(struct si_context *sctx,
struct si_resource *bu
radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
radeon_emit(cs, 0);
}
static void si_buffer_do_flush_region(struct pipe_context *ctx,
struct pipe_transfer *transfer,
const struct pipe_box *box)
{
struct si_context *sctx = (struct si_context*)ctx;
struct si_transfer *stransfer = (struct si_transfer*)transfer;
- struct si_resource *rbuffer = si_resource(transfer->resource);
+ struct si_resource *buf = si_resource(transfer->resource);
if (stransfer->offset == SI_TRANSFER_SPECIAL_OFFSET_USE_CPU_ALLOC) {
- si_buffer_write_data(sctx, rbuffer, box->x, box->width,
+ si_buffer_write_data(sctx, buf, box->x, box->width,
stransfer->u.cpu);
} else if (stransfer->u.staging) {
/* Copy the staging buffer into the original one. */
si_copy_buffer(sctx, transfer->resource,
&stransfer->u.staging->b.b, box->x,
stransfer->offset + box->x %
SI_MAP_BUFFER_ALIGNMENT,
box->width);
}
- util_range_add(&rbuffer->valid_buffer_range, box->x,
+ util_range_add(&buf->valid_buffer_range, box->x,
box->x + box->width);
}
static void si_buffer_flush_region(struct pipe_context *ctx,
struct pipe_transfer *transfer,
const struct pipe_box *rel_box)
{
unsigned required_usage = PIPE_TRANSFER_WRITE |
PIPE_TRANSFER_FLUSH_EXPLICIT;
@@ -641,59 +641,59 @@ static const struct u_resource_vtbl si_buffer_vtbl =
si_buffer_destroy, /* resource_destroy */
si_buffer_transfer_map, /* transfer_map */
si_buffer_flush_region, /* transfer_flush_region */
si_buffer_transfer_unmap, /* transfer_unmap */
};
static struct si_resource *
si_alloc_buffer_struct(struct pipe_screen *screen,
const struct pipe_resource *templ)
{
- struct si_resource *rbuffer;
+ struct si_resource *buf;
- rbuffer = MALLOC_STRUCT(si_resource);
+ buf = MALLOC_STRUCT(si_resource);
- rbuffer->b.b = *templ;
- rbuffer->b.b.next = NULL;
- pipe_reference_init(&rbuffer->b.b.reference, 1);
- rbuffer->b.b.screen = screen;
+ buf->b.b = *templ;
+ buf->b.b.next = NULL;
+ pipe_reference_init(&buf->b.b.reference, 1);
+ buf->b.b.screen = screen;
- rbuffer->b.vtbl = &si_buffer_vtbl;
- threaded_resource_init(&rbuffer->b.b);
+ buf->b.vtbl = &si_buffer_vtbl;
+ threaded_resource_init(&buf->b.b);
- rbuffer->buf = NULL;
- rbuffer->bind_history = 0;
- rbuffer->TC_L2_dirty = false;
- util_range_init(&rbuffer->valid_buffer_range);
- return rbuffer;
+ buf->buf = NULL;
+ buf->bind_history = 0;
+ buf->TC_L2_dirty = false;
+ util_range_init(&buf->valid_buffer_range);
+ return buf;
}
static struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
const struct pipe_resource *templ,
unsigned alignment)
{
struct si_screen *sscreen = (struct si_screen*)screen;
- struct si_resource *rbuffer = si_alloc_buffer_struct(screen, templ);
+ struct si_resource *buf = si_alloc_buffer_struct(screen, templ);
if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
- rbuffer->b.b.flags |= SI_RESOURCE_FLAG_UNMAPPABLE;
+ buf->b.b.flags |= SI_RESOURCE_FLAG_UNMAPPABLE;
- si_init_resource_fields(sscreen, rbuffer, templ->width0, alignment);
+ si_init_resource_fields(sscreen, buf, templ->width0, alignment);
if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
- rbuffer->flags |= RADEON_FLAG_SPARSE;
+ buf->flags |= RADEON_FLAG_SPARSE;
- if (!si_alloc_resource(sscreen, rbuffer)) {
- FREE(rbuffer);
+ if (!si_alloc_resource(sscreen, buf)) {
+ FREE(buf);
return NULL;
}
- return &rbuffer->b.b;
+ return &buf->b.b;
}
struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
unsigned flags, unsigned usage,
unsigned size, unsigned
alignment)
{
struct pipe_resource buffer;
memset(&buffer, 0, sizeof buffer);
buffer.target = PIPE_BUFFER;
@@ -716,40 +716,40 @@ struct si_resource *si_aligned_buffer_create(struct
pipe_screen *screen,
size, alignment));
}
static struct pipe_resource *
si_buffer_from_user_memory(struct pipe_screen *screen,
const struct pipe_resource *templ,
void *user_memory)
{
struct si_screen *sscreen = (struct si_screen*)screen;
struct radeon_winsys *ws = sscreen->ws;
- struct si_resource *rbuffer = si_alloc_buffer_struct(screen, templ);
+ struct si_resource *buf = si_alloc_buffer_struct(screen, templ);
- rbuffer->domains = RADEON_DOMAIN_GTT;
- rbuffer->flags = 0;
- rbuffer->b.is_user_ptr = true;
- util_range_add(&rbuffer->valid_buffer_range, 0, templ->width0);
- util_range_add(&rbuffer->b.valid_buffer_range, 0, templ->width0);
+ buf->domains = RADEON_DOMAIN_GTT;
+ buf->flags = 0;
+ buf->b.is_user_ptr = true;
+ util_range_add(&buf->valid_buffer_range, 0, templ->width0);
+ util_range_add(&buf->b.valid_buffer_range, 0, templ->width0);
/* Convert a user pointer to a buffer. */
- rbuffer->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0);
- if (!rbuffer->buf) {
- FREE(rbuffer);
+ buf->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0);
+ if (!buf->buf) {
+ FREE(buf);
return NULL;
}
- rbuffer->gpu_address = ws->buffer_get_virtual_address(rbuffer->buf);
- rbuffer->vram_usage = 0;
- rbuffer->gart_usage = templ->width0;
+ buf->gpu_address = ws->buffer_get_virtual_address(buf->buf);
+ buf->vram_usage = 0;
+ buf->gart_usage = templ->width0;
- return &rbuffer->b.b;
+ return &buf->b.b;
}
static struct pipe_resource *si_resource_create(struct pipe_screen *screen,
const struct pipe_resource
*templ)
{
if (templ->target == PIPE_BUFFER) {
return si_buffer_create(screen, templ, 256);
} else {
return si_texture_create(screen, templ);
}
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 04b366a1416..9900cde51ee 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -1119,36 +1119,36 @@ bool si_upload_vertex_buffer_descriptors(struct
si_context *sctx)
sctx->vb_descriptors_gpu_list = ptr;
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
sctx->vb_descriptors_buffer,
RADEON_USAGE_READ,
RADEON_PRIO_DESCRIPTORS);
assert(count <= SI_MAX_ATTRIBS);
for (i = 0; i < count; i++) {
struct pipe_vertex_buffer *vb;
- struct si_resource *rbuffer;
+ struct si_resource *buf;
unsigned vbo_index = velems->vertex_buffer_index[i];
uint32_t *desc = &ptr[i*4];
vb = &sctx->vertex_buffer[vbo_index];
- rbuffer = si_resource(vb->buffer.resource);
- if (!rbuffer) {
+ buf = si_resource(vb->buffer.resource);
+ if (!buf) {
memset(desc, 0, 16);
continue;
}
int64_t offset = (int64_t)((int)vb->buffer_offset) +
velems->src_offset[i];
- uint64_t va = rbuffer->gpu_address + offset;
+ uint64_t va = buf->gpu_address + offset;
- int64_t num_records = (int64_t)rbuffer->b.b.width0 - offset;
+ int64_t num_records = (int64_t)buf->b.b.width0 - offset;
if (sctx->chip_class != VI && vb->stride) {
/* Round up by rounding down and adding 1 */
num_records = (num_records - velems->format_size[i]) /
vb->stride + 1;
}
assert(num_records >= 0 && num_records <= UINT_MAX);
desc[0] = va;
desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
S_008F04_STRIDE(vb->stride);
@@ -1182,30 +1182,30 @@ si_const_and_shader_buffer_descriptors_idx(unsigned
shader)
return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS;
}
static struct si_descriptors *
si_const_and_shader_buffer_descriptors(struct si_context *sctx, unsigned
shader)
{
return
&sctx->descriptors[si_const_and_shader_buffer_descriptors_idx(shader)];
}
-void si_upload_const_buffer(struct si_context *sctx, struct si_resource
**rbuffer,
+void si_upload_const_buffer(struct si_context *sctx, struct si_resource **buf,
const uint8_t *ptr, unsigned size, uint32_t
*const_offset)
{
void *tmp;
u_upload_alloc(sctx->b.const_uploader, 0, size,
si_optimal_tcc_alignment(sctx, size),
const_offset,
- (struct pipe_resource**)rbuffer, &tmp);
- if (*rbuffer)
+ (struct pipe_resource**)buf, &tmp);
+ if (*buf)
util_memcpy_cpu_to_le32(tmp, ptr, size);
}
static void si_set_constant_buffer(struct si_context *sctx,
struct si_buffer_resources *buffers,
unsigned descriptors_idx,
uint slot, const struct pipe_constant_buffer
*input)
{
struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
assert(slot < descs->num_elements);
@@ -1616,127 +1616,127 @@ static void si_reset_buffer_resources(struct
si_context *sctx,
}
}
}
/* Update all resource bindings where the buffer is bound, including
* all resource descriptors. This is invalidate_buffer without
* the invalidation. */
void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf,
uint64_t old_va)
{
- struct si_resource *rbuffer = si_resource(buf);
+ struct si_resource *buffer = si_resource(buf);
unsigned i, shader;
unsigned num_elems = sctx->vertex_elements ?
sctx->vertex_elements->count : 0;
/* We changed the buffer, now we need to bind it where the old one
* was bound. This consists of 2 things:
* 1) Updating the resource descriptor and dirtying it.
* 2) Adding a relocation to the CS, so that it's usable.
*/
/* Vertex buffers. */
- if (rbuffer->bind_history & PIPE_BIND_VERTEX_BUFFER) {
+ if (buffer->bind_history & PIPE_BIND_VERTEX_BUFFER) {
for (i = 0; i < num_elems; i++) {
int vb = sctx->vertex_elements->vertex_buffer_index[i];
if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
continue;
if (!sctx->vertex_buffer[vb].buffer.resource)
continue;
if (sctx->vertex_buffer[vb].buffer.resource == buf) {
sctx->vertex_buffers_dirty = true;
break;
}
}
}
/* Streamout buffers. (other internal buffers can't be invalidated) */
- if (rbuffer->bind_history & PIPE_BIND_STREAM_OUTPUT) {
+ if (buffer->bind_history & PIPE_BIND_STREAM_OUTPUT) {
for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
struct si_buffer_resources *buffers = &sctx->rw_buffers;
struct si_descriptors *descs =
&sctx->descriptors[SI_DESCS_RW_BUFFERS];
if (buffers->buffers[i] != buf)
continue;
si_desc_reset_buffer_offset(descs->list + i*4,
old_va, buf);
sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
radeon_add_to_gfx_buffer_list_check_mem(sctx,
- rbuffer,
buffers->shader_usage,
+ buffer,
buffers->shader_usage,
RADEON_PRIO_SHADER_RW_BUFFER,
true);
/* Update the streamout state. */
if (sctx->streamout.begin_emitted)
si_emit_streamout_end(sctx);
sctx->streamout.append_bitmask =
sctx->streamout.enabled_mask;
si_streamout_buffers_dirty(sctx);
}
}
/* Constant and shader buffers. */
- if (rbuffer->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
+ if (buffer->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
for (shader = 0; shader < SI_NUM_SHADERS; shader++)
si_reset_buffer_resources(sctx,
&sctx->const_and_shader_buffers[shader],
si_const_and_shader_buffer_descriptors_idx(shader),
u_bit_consecutive(SI_NUM_SHADER_BUFFERS, SI_NUM_CONST_BUFFERS),
buf, old_va,
sctx->const_and_shader_buffers[shader].shader_usage_constbuf,
sctx->const_and_shader_buffers[shader].priority_constbuf);
}
- if (rbuffer->bind_history & PIPE_BIND_SHADER_BUFFER) {
+ if (buffer->bind_history & PIPE_BIND_SHADER_BUFFER) {
for (shader = 0; shader < SI_NUM_SHADERS; shader++)
si_reset_buffer_resources(sctx,
&sctx->const_and_shader_buffers[shader],
si_const_and_shader_buffer_descriptors_idx(shader),
u_bit_consecutive(0,
SI_NUM_SHADER_BUFFERS),
buf, old_va,
sctx->const_and_shader_buffers[shader].shader_usage,
sctx->const_and_shader_buffers[shader].priority);
}
- if (rbuffer->bind_history & PIPE_BIND_SAMPLER_VIEW) {
+ if (buffer->bind_history & PIPE_BIND_SAMPLER_VIEW) {
/* Texture buffers - update bindings. */
for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
struct si_samplers *samplers = &sctx->samplers[shader];
struct si_descriptors *descs =
si_sampler_and_image_descriptors(sctx, shader);
unsigned mask = samplers->enabled_mask;
while (mask) {
unsigned i = u_bit_scan(&mask);
if (samplers->views[i]->texture == buf) {
unsigned desc_slot =
si_get_sampler_slot(i);
si_desc_reset_buffer_offset(descs->list
+
desc_slot *
16 + 4,
old_va,
buf);
sctx->descriptors_dirty |=
1u <<
si_sampler_and_image_descriptors_idx(shader);
radeon_add_to_gfx_buffer_list_check_mem(sctx,
-
rbuffer, RADEON_USAGE_READ,
+
buffer, RADEON_USAGE_READ,
RADEON_PRIO_SAMPLER_BUFFER,
true);
}
}
}
}
/* Shader images */
- if (rbuffer->bind_history & PIPE_BIND_SHADER_IMAGE) {
+ if (buffer->bind_history & PIPE_BIND_SHADER_IMAGE) {
for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
struct si_images *images = &sctx->images[shader];
struct si_descriptors *descs =
si_sampler_and_image_descriptors(sctx, shader);
unsigned mask = images->enabled_mask;
while (mask) {
unsigned i = u_bit_scan(&mask);
if (images->views[i].resource == buf) {
@@ -1745,77 +1745,77 @@ void si_rebind_buffer(struct si_context *sctx, struct
pipe_resource *buf,
if (images->views[i].access &
PIPE_IMAGE_ACCESS_WRITE)
si_mark_image_range_valid(&images->views[i]);
si_desc_reset_buffer_offset(
descs->list + desc_slot * 8 + 4,
old_va, buf);
sctx->descriptors_dirty |=
1u <<
si_sampler_and_image_descriptors_idx(shader);
radeon_add_to_gfx_buffer_list_check_mem(
- sctx, rbuffer,
+ sctx, buffer,
RADEON_USAGE_READWRITE,
RADEON_PRIO_SAMPLER_BUFFER,
true);
}
}
}
}
/* Bindless texture handles */
- if (rbuffer->texture_handle_allocated) {
+ if (buffer->texture_handle_allocated) {
struct si_descriptors *descs = &sctx->bindless_descriptors;
util_dynarray_foreach(&sctx->resident_tex_handles,
struct si_texture_handle *, tex_handle) {
struct pipe_sampler_view *view = (*tex_handle)->view;
unsigned desc_slot = (*tex_handle)->desc_slot;
if (view->texture == buf) {
- si_set_buf_desc_address(rbuffer,
+ si_set_buf_desc_address(buffer,
view->u.buf.offset,
descs->list +
desc_slot * 16 + 4);
(*tex_handle)->desc_dirty = true;
sctx->bindless_descriptors_dirty = true;
radeon_add_to_gfx_buffer_list_check_mem(
- sctx, rbuffer,
+ sctx, buffer,
RADEON_USAGE_READ,
RADEON_PRIO_SAMPLER_BUFFER, true);
}
}
}
/* Bindless image handles */
- if (rbuffer->image_handle_allocated) {
+ if (buffer->image_handle_allocated) {
struct si_descriptors *descs = &sctx->bindless_descriptors;
util_dynarray_foreach(&sctx->resident_img_handles,
struct si_image_handle *, img_handle) {
struct pipe_image_view *view = &(*img_handle)->view;
unsigned desc_slot = (*img_handle)->desc_slot;
if (view->resource == buf) {
if (view->access & PIPE_IMAGE_ACCESS_WRITE)
si_mark_image_range_valid(view);
- si_set_buf_desc_address(rbuffer,
+ si_set_buf_desc_address(buffer,
view->u.buf.offset,
descs->list +
desc_slot * 16 + 4);
(*img_handle)->desc_dirty = true;
sctx->bindless_descriptors_dirty = true;
radeon_add_to_gfx_buffer_list_check_mem(
- sctx, rbuffer,
+ sctx, buffer,
RADEON_USAGE_READWRITE,
RADEON_PRIO_SAMPLER_BUFFER, true);
}
}
}
}
static void si_upload_bindless_descriptor(struct si_context *sctx,
unsigned desc_slot,
unsigned num_dwords)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index ad04a803c0a..352d1ba3034 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -1632,29 +1632,29 @@ radeon_cs_memory_below_limit(struct si_screen *screen,
*
* All buffers used by a CS must be added to the list. This tells the kernel
* driver which buffers are used by GPU commands. Other buffers can
* be swapped out (not accessible) during execution.
*
* The buffer list becomes empty after every context flush and must be
* rebuilt.
*/
static inline void radeon_add_to_buffer_list(struct si_context *sctx,
struct radeon_cmdbuf *cs,
- struct si_resource *rbo,
+ struct si_resource *bo,
enum radeon_bo_usage usage,
enum radeon_bo_priority priority)
{
assert(usage);
sctx->ws->cs_add_buffer(
- cs, rbo->buf,
+ cs, bo->buf,
(enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
- rbo->domains, priority);
+ bo->domains, priority);
}
/**
* Same as above, but also checks memory usage and flushes the context
* accordingly.
*
* When this SHOULD NOT be used:
*
* - if si_context_add_resource_size has been called for the buffer
* followed by *_need_cs_space for checking the memory usage
@@ -1662,28 +1662,28 @@ static inline void radeon_add_to_buffer_list(struct
si_context *sctx,
* - if si_need_dma_space has been called for the buffer
*
* - when emitting state packets and draw packets (because preceding packets
* can't be re-emitted at that point)
*
* - if shader resource "enabled_mask" is not up-to-date or there is
* a different constraint disallowing a context flush
*/
static inline void
radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
- struct si_resource *rbo,
+ struct si_resource *bo,
enum radeon_bo_usage usage,
enum radeon_bo_priority priority,
bool check_mem)
{
if (check_mem &&
!radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
- sctx->vram + rbo->vram_usage,
- sctx->gtt + rbo->gart_usage))
+ sctx->vram + bo->vram_usage,
+ sctx->gtt + bo->gart_usage))
si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW,
NULL);
- radeon_add_to_buffer_list(sctx, sctx->gfx_cs, rbo, usage, priority);
+ radeon_add_to_buffer_list(sctx, sctx->gfx_cs, bo, usage, priority);
}
#define PRINT_ERR(fmt, args...) \
fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__,
##args)
#endif
diff --git a/src/gallium/drivers/radeonsi/si_state.h
b/src/gallium/drivers/radeonsi/si_state.h
index fb9cba67c21..767e789276a 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -458,21 +458,21 @@ void si_set_ring_buffer(struct si_context *sctx, uint
slot,
unsigned stride, unsigned num_records,
bool add_tid, bool swizzle,
unsigned element_size, unsigned index_stride, uint64_t
offset);
void si_init_all_descriptors(struct si_context *sctx);
bool si_upload_vertex_buffer_descriptors(struct si_context *sctx);
bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
bool si_upload_compute_shader_descriptors(struct si_context *sctx);
void si_release_all_descriptors(struct si_context *sctx);
void si_all_descriptors_begin_new_cs(struct si_context *sctx);
void si_all_resident_buffers_begin_new_cs(struct si_context *sctx);
-void si_upload_const_buffer(struct si_context *sctx, struct si_resource
**rbuffer,
+void si_upload_const_buffer(struct si_context *sctx, struct si_resource **buf,
const uint8_t *ptr, unsigned size, uint32_t
*const_offset);
void si_update_all_texture_descriptors(struct si_context *sctx);
void si_shader_change_notify(struct si_context *sctx);
void si_update_needs_color_decompress_masks(struct si_context *sctx);
void si_emit_graphics_shader_pointers(struct si_context *sctx);
void si_emit_compute_shader_pointers(struct si_context *sctx);
void si_set_rw_buffer(struct si_context *sctx,
uint slot, const struct pipe_constant_buffer *input);
void si_set_rw_shader_buffer(struct si_context *sctx, uint slot,
const struct pipe_shader_buffer *sbuffer);
diff --git a/src/gallium/drivers/radeonsi/si_state_streamout.c
b/src/gallium/drivers/radeonsi/si_state_streamout.c
index 64994139c5f..2bf6862c89b 100644
--- a/src/gallium/drivers/radeonsi/si_state_streamout.c
+++ b/src/gallium/drivers/radeonsi/si_state_streamout.c
@@ -36,42 +36,42 @@ static inline void si_so_target_reference(struct
si_streamout_target **dst,
}
static struct pipe_stream_output_target *
si_create_so_target(struct pipe_context *ctx,
struct pipe_resource *buffer,
unsigned buffer_offset,
unsigned buffer_size)
{
struct si_context *sctx = (struct si_context *)ctx;
struct si_streamout_target *t;
- struct si_resource *rbuffer = si_resource(buffer);
+ struct si_resource *buf = si_resource(buffer);
t = CALLOC_STRUCT(si_streamout_target);
if (!t) {
return NULL;
}
u_suballocator_alloc(sctx->allocator_zeroed_memory, 4, 4,
&t->buf_filled_size_offset,
(struct pipe_resource**)&t->buf_filled_size);
if (!t->buf_filled_size) {
FREE(t);
return NULL;
}
t->b.reference.count = 1;
t->b.context = ctx;
pipe_resource_reference(&t->b.buffer, buffer);
t->b.buffer_offset = buffer_offset;
t->b.buffer_size = buffer_size;
- util_range_add(&rbuffer->valid_buffer_range, buffer_offset,
+ util_range_add(&buf->valid_buffer_range, buffer_offset,
buffer_offset + buffer_size);
return &t->b;
}
static void si_so_target_destroy(struct pipe_context *ctx,
struct pipe_stream_output_target *target)
{
struct si_streamout_target *t = (struct si_streamout_target*)target;
pipe_resource_reference(&t->b.buffer, NULL);
si_resource_reference(&t->buf_filled_size, NULL);
--
2.17.1
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