From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeon/radeon_uvd_enc.h | 2 +-
src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 10 +++++-----
src/gallium/drivers/radeonsi/si_compute.c | 4 ++--
src/gallium/drivers/radeonsi/si_gpu_load.c | 4 ++--
src/gallium/drivers/radeonsi/si_texture.c | 2 +-
5 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.h
b/src/gallium/drivers/radeon/radeon_uvd_enc.h
index 63176d264c2..52e7ae3c0a9 100644
--- a/src/gallium/drivers/radeon/radeon_uvd_enc.h
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.h
@@ -457,13 +457,13 @@ struct radeon_uvd_encoder
unsigned byte_index;
unsigned bits_output;
uint32_t total_task_size;
uint32_t *p_task_size;
bool emulation_prevention;
bool need_feedback;
};
void radeon_uvd_enc_1_1_init(struct radeon_uvd_encoder *enc);
-bool si_radeon_uvd_enc_supported(struct si_screen *rscreen);
+bool si_radeon_uvd_enc_supported(struct si_screen *sscreen);
#endif // _RADEON_UVD_ENC_H
diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
index ddb219792ae..1f41b09472f 100644
--- a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
@@ -828,24 +828,24 @@ radeon_uvd_enc_slice_header_hevc(struct
radeon_uvd_encoder *enc)
RADEON_ENC_CS(instruction[j]);
RADEON_ENC_CS(num_bits[j]);
}
RADEON_ENC_END();
}
static void
radeon_uvd_enc_ctx(struct radeon_uvd_encoder *enc)
{
- struct si_screen *rscreen = (struct si_screen *) enc->screen;
+ struct si_screen *sscreen = (struct si_screen *) enc->screen;
enc->enc_pic.ctx_buf.swizzle_mode = 0;
- if (rscreen->info.chip_class < GFX9) {
+ if (sscreen->info.chip_class < GFX9) {
enc->enc_pic.ctx_buf.rec_luma_pitch =
(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe);
enc->enc_pic.ctx_buf.rec_chroma_pitch =
(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe);
}
else {
enc->enc_pic.ctx_buf.rec_luma_pitch =
enc->luma->u.gfx9.surf_pitch * enc->luma->bpe;
enc->enc_pic.ctx_buf.rec_chroma_pitch =
enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe;
@@ -943,41 +943,41 @@ radeon_uvd_enc_rc_per_pic(struct radeon_uvd_encoder *enc,
RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size);
RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data);
RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable);
RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd);
RADEON_ENC_END();
}
static void
radeon_uvd_enc_encode_params_hevc(struct radeon_uvd_encoder *enc)
{
- struct si_screen *rscreen = (struct si_screen *) enc->screen;
+ struct si_screen *sscreen = (struct si_screen *) enc->screen;
switch (enc->enc_pic.picture_type) {
case PIPE_H265_ENC_PICTURE_TYPE_I:
case PIPE_H265_ENC_PICTURE_TYPE_IDR:
enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_I;
break;
case PIPE_H265_ENC_PICTURE_TYPE_P:
enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_P;
break;
case PIPE_H265_ENC_PICTURE_TYPE_SKIP:
enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_P_SKIP;
break;
case PIPE_H265_ENC_PICTURE_TYPE_B:
enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_B;
break;
default:
enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_I;
}
enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
- if (rscreen->info.chip_class < GFX9) {
+ if (sscreen->info.chip_class < GFX9) {
enc->enc_pic.enc_params.input_pic_luma_pitch =
(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe);
enc->enc_pic.enc_params.input_pic_chroma_pitch =
(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe);
}
else {
enc->enc_pic.enc_params.input_pic_luma_pitch =
enc->luma->u.gfx9.surf_pitch * enc->luma->bpe;
enc->enc_pic.enc_params.input_pic_chroma_pitch =
enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe;
@@ -991,21 +991,21 @@ radeon_uvd_enc_encode_params_hevc(struct
radeon_uvd_encoder *enc)
enc->enc_pic.enc_params.reference_picture_index =
(enc->enc_pic.frame_num - 1) % 2;
enc->enc_pic.enc_params.reconstructed_picture_index =
enc->enc_pic.frame_num % 2;
RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_ENCODE_PARAMS);
RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
- if (rscreen->info.chip_class < GFX9) {
+ if (sscreen->info.chip_class < GFX9) {
RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->luma->u.legacy.level[0].offset);
RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->chroma->u.legacy.level[0].offset);
}
else {
RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->luma->u.gfx9.surf_offset);
RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->chroma->u.gfx9.surf_offset);
diff --git a/src/gallium/drivers/radeonsi/si_compute.c
b/src/gallium/drivers/radeonsi/si_compute.c
index 9ce635366aa..89c9179fef8 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -25,23 +25,23 @@
#include "tgsi/tgsi_parse.h"
#include "util/u_async_debug.h"
#include "util/u_memory.h"
#include "util/u_upload_mgr.h"
#include "amd_kernel_code_t.h"
#include "si_build_pm4.h"
#include "si_compute.h"
-#define COMPUTE_DBG(rscreen, fmt, args...) \
+#define COMPUTE_DBG(sscreen, fmt, args...) \
do { \
- if ((rscreen->debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt,
##args); \
+ if ((sscreen->debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt,
##args); \
} while (0);
struct dispatch_packet {
uint16_t header;
uint16_t setup;
uint16_t workgroup_size_x;
uint16_t workgroup_size_y;
uint16_t workgroup_size_z;
uint16_t reserved0;
uint32_t grid_size_x;
diff --git a/src/gallium/drivers/radeonsi/si_gpu_load.c
b/src/gallium/drivers/radeonsi/si_gpu_load.c
index 8c457b30eaa..481438f37bb 100644
--- a/src/gallium/drivers/radeonsi/si_gpu_load.c
+++ b/src/gallium/drivers/radeonsi/si_gpu_load.c
@@ -206,22 +206,22 @@ static unsigned si_end_mmio_counter(struct si_screen
*sscreen,
return busy*100 / (busy + idle);
} else {
union si_mmio_counters counters;
memset(&counters, 0, sizeof(counters));
si_update_mmio_counters(sscreen, &counters);
return counters.array[busy_index] ? 100 : 0;
}
}
-#define BUSY_INDEX(rscreen, field) (&rscreen->mmio_counters.named.field.busy -
\
- rscreen->mmio_counters.array)
+#define BUSY_INDEX(sscreen, field) (&sscreen->mmio_counters.named.field.busy -
\
+ sscreen->mmio_counters.array)
static unsigned busy_index_from_type(struct si_screen *sscreen,
unsigned type)
{
switch (type) {
case SI_QUERY_GPU_LOAD:
return BUSY_INDEX(sscreen, gpu);
case SI_QUERY_GPU_SHADERS_BUSY:
return BUSY_INDEX(sscreen, spi);
case SI_QUERY_GPU_TA_BUSY:
diff --git a/src/gallium/drivers/radeonsi/si_texture.c
b/src/gallium/drivers/radeonsi/si_texture.c
index 9c26ad693d1..dcd6ffbb875 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -449,21 +449,21 @@ static bool si_texture_discard_dcc(struct si_screen
*sscreen,
* If context 1 disables DCC and context 2 has queued commands that write
* to the texture via CB with DCC enabled, and the order of operations is
* as follows:
* context 2 queues draw calls rendering to the texture, but doesn't flush
* context 1 disables DCC and flushes
* context 1 & 2 reset descriptors and FB state
* context 2 flushes (new compressed tiles written by the draw calls)
* context 1 & 2 read garbage, because DCC is disabled, yet there are
* compressed tiled
*
- * \param sctx the current context if you have one, or rscreen->aux_context
+ * \param sctx the current context if you have one, or sscreen->aux_context
* if you don't.
*/
bool si_texture_disable_dcc(struct si_context *sctx,
struct si_texture *tex)
{
struct si_screen *sscreen = sctx->screen;
if (!si_can_disable_dcc(tex))
return false;
--
2.17.1
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
