---
src/gallium/drivers/radeon/AMDGPUISelLowering.cpp | 3 +--
src/gallium/drivers/radeon/AMDGPUIntrinsics.td | 1 -
src/gallium/drivers/radeon/AMDILIntrinsics.td | 2 --
src/gallium/drivers/radeon/R600Instructions.td | 2 +-
src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 8 ++++----
5 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
index d37df6b..6c69c0b 100644
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
@@ -39,6 +39,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM)
:
setOperationAction(ISD::FABS, MVT::f32, Legal);
setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
setOperationAction(ISD::FRINT, MVT::f32, Legal);
+ setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
setOperationAction(ISD::UDIV, MVT::i32, Expand);
setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
@@ -137,8 +138,6 @@ SDValue
AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
case AMDGPUIntrinsic::AMDGPU_umin:
return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
Op.getOperand(2));
- case AMDGPUIntrinsic::AMDIL_round_nearest:
- return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
}
}
diff --git a/src/gallium/drivers/radeon/AMDGPUIntrinsics.td
b/src/gallium/drivers/radeon/AMDGPUIntrinsics.td
index eaca4cf..70bf2af 100644
--- a/src/gallium/drivers/radeon/AMDGPUIntrinsics.td
+++ b/src/gallium/drivers/radeon/AMDGPUIntrinsics.td
@@ -43,7 +43,6 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in {
def int_AMDGPU_txq : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_AMDGPU_txd : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
def int_AMDGPU_txl : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty,
llvm_i32_ty], [IntrNoMem]>;
- def int_AMDGPU_trunc : Intrinsic<[llvm_float_ty], [llvm_float_ty],
[IntrNoMem]>;
def int_AMDGPU_ddx : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_AMDGPU_ddy : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_AMDGPU_imax : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
[IntrNoMem]>;
diff --git a/src/gallium/drivers/radeon/AMDILIntrinsics.td
b/src/gallium/drivers/radeon/AMDILIntrinsics.td
index 3f9e20f..e7a71d4 100644
--- a/src/gallium/drivers/radeon/AMDILIntrinsics.td
+++ b/src/gallium/drivers/radeon/AMDILIntrinsics.td
@@ -142,8 +142,6 @@ let TargetPrefix = "AMDIL", isTarget = 1 in {
TernaryIntFloat;
def int_AMDIL_pireduce : GCCBuiltin<"__amdil_pireduce">,
UnaryIntFloat;
- def int_AMDIL_round_nearest : GCCBuiltin<"__amdil_round_nearest">,
- UnaryIntFloat;
def int_AMDIL_round_neginf : GCCBuiltin<"__amdil_round_neginf">,
UnaryIntFloat;
def int_AMDIL_round_zero : GCCBuiltin<"__amdil_round_zero">,
diff --git a/src/gallium/drivers/radeon/R600Instructions.td
b/src/gallium/drivers/radeon/R600Instructions.td
index 120a71c..29826fa 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -384,7 +384,7 @@ def FRACT : R600_1OP <
def TRUNC : R600_1OP <
0x11, "TRUNC",
- [(set R600_Reg32:$dst, (int_AMDGPU_trunc R600_Reg32:$src))]
+ [(set R600_Reg32:$dst, (ftrunc R600_Reg32:$src))]
>;
def CEIL : R600_1OP <
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 57ec372..1a8154a 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -1099,8 +1099,8 @@ void radeon_llvm_context_init(struct radeon_llvm_context
* ctx)
bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp;
bld_base->op_actions[TGSI_OPCODE_ISGE].emit = emit_icmp;
bld_base->op_actions[TGSI_OPCODE_ISLT].emit = emit_icmp;
- bld_base->op_actions[TGSI_OPCODE_ROUND].emit =
build_tgsi_intrinsic_nomem;
- bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name =
"llvm.AMDIL.round.nearest.";
+ bld_base->op_actions[TGSI_OPCODE_ROUND].emit =
build_tgsi_intrinsic_readonly;
+ bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = "rint";
bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.AMDIL.min.";
bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
@@ -1187,8 +1187,8 @@ void radeon_llvm_context_init(struct radeon_llvm_context
* ctx)
bld_base->op_actions[TGSI_OPCODE_TXL].intr_name = "llvm.AMDGPU.txl";
bld_base->op_actions[TGSI_OPCODE_TXP].fetch_args = txp_fetch_args;
bld_base->op_actions[TGSI_OPCODE_TXP].intr_name = "llvm.AMDGPU.tex";
- bld_base->op_actions[TGSI_OPCODE_TRUNC].emit =
build_tgsi_intrinsic_nomem;
- bld_base->op_actions[TGSI_OPCODE_TRUNC].intr_name = "llvm.AMDGPU.trunc";
+ bld_base->op_actions[TGSI_OPCODE_TRUNC].emit =
build_tgsi_intrinsic_readonly;
+ bld_base->op_actions[TGSI_OPCODE_TRUNC].intr_name = "trunc";
bld_base->rsq_action.emit = build_tgsi_intrinsic_nomem;
bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq";
--
1.7.11.4
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