Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 37 +++++++++++++++++------
1 file changed, 27 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 759fef5..186b4ac 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -298,6 +298,15 @@ gen7_update_texture_surface(struct gl_context *ctx,
intelObj->_Format,
sampler->sRGBDecode);
+ if (brw_use_stencil_index_mode(brw, tObj)) {
+ if (firstImage->_BaseFormat == GL_DEPTH_STENCIL)
+ mt = mt->stencil_mt;
+ brw_configure_w_tiled(mt, false, &width, &height, &pitch,
+ &tiling, &tex_format);
+ min_lod = mt->first_level;
+ mip_count = 0;
+ }
+
if (for_gather && tex_format == BRW_SURFACEFORMAT_R32G32_FLOAT)
tex_format = BRW_SURFACEFORMAT_R32G32_FLOAT_LD;
@@ -323,7 +332,10 @@ gen7_update_texture_surface(struct gl_context *ctx,
uint32_t effective_depth = (tObj->Immutable && tObj->Target !=
GL_TEXTURE_3D)
? tObj->NumLayers : mt->logical_depth0;
- if (mt->array_spacing_lod0)
+ /* Program accesses stencil mip-levels manually and the surface is
+ * configured as if there was only one level.
+ */
+ if (mt->array_spacing_lod0 || is_stencil(mt))
surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
@@ -489,14 +501,17 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
/* Render targets can't use IMS layout. Stencil in turn gets configured as
* single sampled and indexed manually by the program.
*/
- if (!is_stencil(irb->mt))
- assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
-
- assert(brw_render_target_supported(brw, rb));
- format = brw->render_target_format[rb_format];
- if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
- _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
- __FUNCTION__, _mesa_get_format_name(rb_format));
+ if (is_stencil(irb->mt)) {
+ brw_configure_w_tiled(irb->mt, true, &width, &height, &pitch,
+ &tiling, &format);
+ } else {
+ assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
+ assert(brw_render_target_supported(brw, rb));
+ format = brw->render_target_format[rb_format];
+ if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
+ _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
+ __FUNCTION__, _mesa_get_format_name(rb_format));
+ }
}
switch (gl_target) {
@@ -534,8 +549,10 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
assert(brw->has_surface_tile_offset);
+ /* Stencil mip-levels are accessed manually by the program. */
surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS) |
- (irb->mt_level - irb->mt->first_level);
+ (is_stencil(irb->mt) ?
+ 0 : (irb->mt_level - irb->mt->first_level));
surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
--
1.8.3.1
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