On sobota, 2 maja 2009 02:50:54 you wrote: > On 02.05.2009 01:53, Maciej Cencora wrote: > > Hi, > > > > this simple patch fixes (for IGP chips, non IGP aren't affected): > > - 8 piglit tests: general/texgen, glean/texCube, mesa/crossbar, > > shaders/fp- kil, texturing/gen-teximage, texturing/gen-texsubimage, > > texturing/lodbias, texturing/texredefine, > > - KDE4 Kwin shadows (when desktop effects use OpenGL backend), > > - #16452 bug, > > - many others... > > > > Could anyone test it on some RS48x cards? > > > > Maciej Cencora > > > > > > ------------------------------------------------------------------------ > > > > From f2c2db095fe908b428ad0dccefc39f078cccb3a6 Mon Sep 17 00:00:00 2001 > > From: Maciej Cencora <[email protected]> > > Date: Sat, 2 May 2009 01:30:23 +0200 > > Subject: [PATCH] r300: set proper texture row alignment for IGP chips > > > > Looks like IGP chips require 64 byte alignment > > --- > > src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 11 ++++++----- > > 1 files changed, 6 insertions(+), 5 deletions(-) > > I'm a bit sceptical that this is correct for all IGP chips, especially > non-r300 versions. Also, note that RADEON_CHIPSET_TCL does not > necessarily mean it's a igp, though IIRC only first gen radeons came in > non-tcl discrete flavors. > > Roland
Yes, you're right. I forgot the code is shared with r100 and r200 drivers. I should probably add new field to radeon_context structure (e.g. tex_row_align) and initialize it during context creation based on chip family. I think RS400, RS600, RS690 and RS740 families needs the 64 bytes alignment, but it would be the best if someone from AMD could confirm this. Maciej Cencora ------------------------------------------------------------------------------ Register Now & Save for Velocity, the Web Performance & Operations Conference from O'Reilly Media. Velocity features a full day of expert-led, hands-on workshops and two days of sessions from industry leaders in dedicated Performance & Operations tracks. Use code vel09scf and Save an extra 15% before 5/3. http://p.sf.net/sfu/velocityconf _______________________________________________ Mesa3d-dev mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/mesa3d-dev
