On Wed, Feb 3, 2010 at 4:42 AM, Luca Barbieri <l...@luca-barbieri.com> wrote:
> I tested this on Windows, using nVidia driver 195 on nv40, and it
> seems we are all partially wrong.
>
> SM3 does indeed allow semantics unrelated to hardware resources.
> However, the semantic indices for any semantic type must be in the
> range 0-15, or D3DX will report a compiler error during shader
> compilation:
> error X2000: syntax error : unexpected token 'dcl_texcoord16'
>
> This is further confirmed by the following lines in d3d9types.h:
> #define MAXD3DDECLUSAGE         D3DDECLUSAGE_SAMPLE
> #define MAXD3DDECLUSAGEINDEX    15
>
> I would guess that these two 4-bit values are combined into an 8-bit
> value that is then passed directly to hardware like r600 which
> supports 8-bit semantic indices in hardware.
> Is this the case on Radeon?
>
> Is the 8-bit semantic table a feature of r300 too or only of r600+?

Only r600+.  r3xx-r5xx is more basic.  You basically set up a table
based on the inputs and outputs.  Order doesn't matter as long as the
table is correct for the vs and ps you are using.  See pages 258-261
for the vertex fetch setup and pages 197-199 for the vs to ps routing
of the r5xx accel guide:
http://www.x.org/docs/AMD/R5xx_Acceleration_v1.4.pdf

Alex

>
> In light of this, it may make sense to do some range limitation ourselves too.
> In particular, a good plan could be limiting all semantic indices to
> 0-15, except GENERIC, which could support a 0-127 range.
> This would allow to both directly take advantage of Radeon hardware,
> and let drivers that need to remap in software do so with direct
> lookup in a small array.
>

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