On Wed, Feb 17, 2010 at 10:39 PM, Francisco Jerez
<curroje...@kemper.freedesktop.org> wrote:
> Module: Mesa
> Branch: master
> Commit: f455ca6490fcb65781b21f81c7117bd923e250d1
> URL:    
> http://cgit.freedesktop.org/mesa/mesa/commit/?id=f455ca6490fcb65781b21f81c7117bd923e250d1
>
> Author: Francisco Jerez <curroje...@riseup.net>
> Date:   Tue Feb 16 17:21:10 2010 +0100
>
> st/mesa: Make the frontbuffer visible on st_flush(PIPE_FLUSH_FRAME).
>
> So far the frontbuffer was only being flushed on st_glFlush and
> st_glFinish, however, a co-state tracker may need to make sure that
> any frontbuffer changes are already on its way to the actual front.
>
> The dri2 state tracker will need this for event-driven GL applications
> to resize properly (It could also be done calling "dri_flush_frontbuffer",
> but that way we would flush unnecessarily in the double-buffered case).
>
> Additionally this patch avoids flushing the mesa rendering cache if
> PIPE_FLUSH_RENDER_CACHE wasn't specified.
>
> ---
>
>  src/mesa/state_tracker/st_cb_flush.c |   15 ++++++---------
>  1 files changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_cb_flush.c 
> b/src/mesa/state_tracker/st_cb_flush.c
> index 1329f80..0ddfce4 100644
> --- a/src/mesa/state_tracker/st_cb_flush.c
> +++ b/src/mesa/state_tracker/st_cb_flush.c
> @@ -91,7 +91,8 @@ display_front_buffer(struct st_context *st)
>  void st_flush( struct st_context *st, uint pipeFlushFlags,
>                struct pipe_fence_handle **fence )
>  {
> -   FLUSH_CURRENT(st->ctx, 0);
> +   if (pipeFlushFlags & PIPE_FLUSH_RENDER_CACHE)
> +      FLUSH_CURRENT(st->ctx, 0);

This is incorrect.  Without this call, st->pipe->flush() will be
called with the VBO buffers still mapped, which is illegal.   This
needs to be undone.

Keith

------------------------------------------------------------------------------
Download Intel&reg; Parallel Studio Eval
Try the new software tools for yourself. Speed compiling, find bugs 
proactively, and fine-tune applications for parallel performance. 
See why Intel Parallel Studio got high marks during beta.
http://p.sf.net/sfu/intel-sw-dev
_______________________________________________
Mesa3d-dev mailing list
Mesa3d-dev@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/mesa3d-dev

Reply via email to