Hi, Yes it should be psu_uart_1. Please use rel-v2018.3 branches from github.com/xilinx tree, we have verified and it works. https://github.com/Xilinx/meta-xilinx-tools/blob/rel-v2018.2/classes/xsctyaml.bbclass#L15-L16
You can use repo command to get the release branches http://www.wiki.xilinx.com/How%20to%20build%20images%20through%20yocto Thanks, Manju From: [email protected] [mailto:[email protected]] On Behalf Of Tomas Thoresen Sent: Wednesday, September 26, 2018 2:04 AM To: [email protected]; [email protected] Subject: Re: [meta-xilinx] Ultra96 UART Hi Simon, If I’m not mistaking, I believe it uses uart1 instead of uart0... So, something like this: YAML_BSP_CONFIG[stdin]="set,psu_uart_1" YAML_BSP_CONFIG[stdout]="set,psu_uart_1" Hope this helps. Cheers, Tomas From: [email protected]<mailto:[email protected]> [mailto:[email protected]] On Behalf Of [email protected]<mailto:[email protected]> Sent: 26 September 2018 09:48 To: [email protected]<mailto:[email protected]> Subject: [meta-xilinx] Ultra96 UART Hi I am trying to get a meta-xilinx/meta-xilinx-tools build (using versions Rocko & rel-v2018.2) to boot on an Ultra96 board. Following the various bits of guidance from this list I have successfully built, and have all the files I would expect in tmp/deploy/images/. The files do not seem to boot - or at least I don't see anything on the serial (via the Avnet serial to USB dongle for the Ultra96). I have read on another forum (http://zedboard.org/content/j6-serial-port-appears-not-be-working) that the default config of the FSBL for the Ultra96 board does not configure the UART properly and indeed using a 'hacked' boot.bin which has been 'fixed' from that forum entry I can boot the board and see output on the UART. My questions are: - Has anyone else successfully booted an Ultra96 using meta-xilinx/meta-xilinx-tools? - If so, did you see anything on the UART? Were any changes made to the FSBL configuration to achieve this? Any comments or guidance gratefully received! Thanks & regards Simon Goda
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