Sean, Many factors affect performance at a given clock speed, including the hardware optimizations of the processor, the compiler's ability to optimize, and the parameters fed to LAME. On an Athlon 800, a specific example might show a throughput of 8 times real time. However, I doubt any current FPGA microprocessor can compare to a superscaler Athlon with three fully pipelined floating point units.
The MIPS benchmark offers little information, as a compiled application may heavily emphasize specific instructions or patterns mostly ignored by the benchmark. Additionally, the instructions used and their throughput depend upon the target architecture and the compiler. An implementation of LAME in a 17 MHz FPGA microprocessor will benefit greatly from custom DSP extensions tuned for LAME. However, with the associated expense of a large FPGA or FPGA array, simply porting LAME to a DSP processor may cost fewer resources and effort. Either way, developing processor specific code for critical FFT, MDCT, or filter functions in LAME will be required for real-time operation on certain chips or processors. Creating a more extensively rewritten version of LAME may further reduce the minimum chip requirements. For example, a fixed point version of LAME may require fewer gates or transistors than a floating point version. Kind regards, - John sean jaye wrote: > > I need any one to answer me Urgently I want to know > the MIPS of lame ,I want to use LAME with a > microprocessor on an FPGA but of_course you know on > FPGA I get low freq about 17 MHZ Is that sufficient > to lame to work correctly > So I need to know its max & min required freq. > > thanks for your help > Sean Jaye _______________________________________________ mp3encoder mailing list [EMAIL PROTECTED] http://minnie.tuhs.org/mailman/listinfo/mp3encoder
