Are you sure about that:
case $host in
x86_64-*-* | i786-*-*)
path_64="x86_64/amd64 x86_64" ;;
k10-*-*)
path_64="x86_64/amd64/k10 x86_64/amd64 x86_64" ;;
nocona-*-* | core2-*-*)
<<-------------------------------------
path_64="x86_64/core2 x86_64" ;;
<<-------------------------------------
esac
Seems to use the core2 code.
Bill.
2009/3/14 Jason Moxham <ja...@njkfrudils.plus.com>:
>
> On Saturday 14 March 2009 17:41:58 Jason Moxham wrote:
>> Early Intel CPUs with Intel 64 lacked LAHF and SAHF instructions available
>> in AMD64 until introduction of Pentium 4 G1 step in December 2005. LAHF and
>> SAHF are load and store instructions, respectively, for certain status
>> flags. These instructions are used for virtualization and floating-point
>> condition handling.
>>
>>
>> I'll find out model numbers soon
>>
>
> No need for MPIR-1.0.0 , all 64bit Pentium's default to nonoca which leads to
> a generic C build.
>
>
>> On Saturday 14 March 2009 17:20:25 Gonzalo Tornaria wrote:
>> > On Sat, Mar 14, 2009 at 1:45 PM, Jason Moxham <ja...@njkfrudils.plus.com>
>>
>> wrote:
>> > > I pretty sure all core2 cpus have lahf,sahf , it's just some Pentium D
>> > > dont have it . You can test the lahf_lm feature bit in cpuid to see if
>> > > it's got it
>> >
>> > Tested in:
>> >
>> > My laptop: model 6 / family 15 (core 2 duo T5300).
>> > My desktop is family 15 / model 6 (pentium D 930).
>> >
>> > The "lahf_lm" feature is present in both according to /proc/cpuinfo.
>> >
>> > Note that the laptop is "low end" core 2 (in the sense it has no VT
>> > extensions). The pentium D is "high end" (in the sense it has VT
>> > extensions --- low end would be pentium D 8xx). Maybe that makes a
>> > difference?
>> >
>> > OTOH, the kvm 64 bit virtual cpu (kvm 72) doesn't seem to know about
>> > the "lahf_lm" (meaning, it won't report it in cpuid, even if the host
>> > processor has it. I assume the instructions would work anyway.)
>> >
>> > Gonzalo
>>
>>
>
>
> >
>
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