Ok, I don't quite understand the statement: "I have since then had the
(USART1 receive) register read during the initialization of the said
peripheral"

Now that the CS is behaving as expected, I am having another problem.
It looks like I'm now experiencing what you are talking about w/ the
Receive register.  It looks like the receive register isn't being
updated prior to the IFG1 RX bit is being set.  This is causing an
immediate read after this bit tests true to be incorrect.  I can add a
single nop() between the IFG1 bit test and the register read to make it
work properly, but I see no mention of this in the TI docs.
Anyone have any other experience w/ reading from SPI?
-Mark


-----Original Message-----
From: mspgcc-users-ad...@lists.sourceforge.net
[mailto:mspgcc-users-ad...@lists.sourceforge.net] On Behalf Of Matti
Ruusunen
Sent: Wednesday, March 05, 2003 8:34 AM
To: mspgcc-users@lists.sourceforge.net
Subject: RE: [Mspgcc-users] UART0 in SPI mode


Hi,

My experiences are similar. 

I fought long with a misbehavior of a piece of harmless USART1 routines
till I found out (the hard and miserable way =) that the receive
register bit became initially set with no reason. So all the external
spi traffic went out of sync because of this. I still don't know for
sure why this happened but I suspect it is related somehow to the other
flags and their activity in the IE1 register, as this did not happen in
my other pieces of code that employed (the same) USART1 routine.

Hence, for reliable operation I have since then had the (USART1 receive)
register read during the initialization of the said peripheral. I
recommend this to others too.

Oh, and the module was/is F149.

Regards,
Matti




======================================================================
Matti Ruusunen               IST International Security Technology Oy
Hardware Designer            Melkonkatu 16A FIN-00210 Helsinki Finland
tel. +358-50-4341321         fax. +358-9-68723681
matti.ruusu...@istsec.fi     http://www.istsec.fi
======================================================================


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