SLAU049C states: "ROSC also allows the DCO to operate at higher frequencies. For example, the internal resistor nominal value is approximately 200 k., allowing the DCO to operate up to approximately 5 MHz. When using an external ROSC of approximately 100 k. the DCO can operate up to approximately 10 MHz. The user should take care to not exceed the maximum MCLK frequency specified in the datasheet, even though the DCO is capable of exceeding it."
Works for me. Regards, Ralf "Steve Underwood" <ste...@coppice.org> schrieb im Newsbeitrag news:3fd7bac6.4040...@coppice.org... > Hi Celso, > > The highest frequency you can get using the internal resistors is about > 4MHz. However, the devices are specified for operation up to 8MHz, and > you can achieve this by attaching an external resistor to P2.5. You need > to program this pin to be an oscillator control pin using the P2SEL > register. The documentation doesn't specify suitable resistor values > properly, so you need to experiment a little. > > Regards, > Steve > > Celso Providelo wrote: > > >Is possible obtain 8 MHz in SMCLK using an 32.768 KHz at X1 ? > > > >I had success until 4,050 MHz, not more than this ... > > > >I'm using the following rotine adapted from Scatterweb : > > > >void dco_init(unsigned long int freq) > >{ > > /*DCO initialisation > > SMCLK = DCOCLK > > MCLK = DCOCLK > > ACLK = 32768 / 8 > > */ > > unsigned int Compare, Oldcapture = 0; > > int delta = freq / 4096; > > > > /* ACLK is divided by 8, RSEL = 7, XT2 is off.*/ > > BCSCTL1 = XT2OFF | DIVA1 | DIVA0 | RSEL2 | RSEL1 | RSEL0; > > > > /* Init FLL to desired frequency using the 32762Hz > > crystal DCO frquenzy */ > > BCSCTL2 = 0x00; > > > > /* Stop WDT */ > > WDTCTL = WDTPW + WDTHOLD; > > > > /* Delay for XTAL to settle */ > > do > > IFG1 &= ~OFIFG; > > while (IFG1 & OFIFG); > > > > /* clear osc. fault int. flag */ > > IFG1 &= ~OFIFG; > > > > /*init TA for capture */ > > CCTL2 = CCIS0 + CM0 + CAP; // Define CCR2, CAP, ACLK > > TACTL = TASSEL1 + TACLR + MC1; // SMCLK, continous mode > > > > while (1) > > { > > while ((CCTL2 & CCIFG) != CCIFG); // Wait until capture occured! > > > > CCTL2 &= ~CCIFG; // Capture occured, clear flag > > Compare = CCR2; // Get current captured SMCLK > > Compare = Compare - Oldcapture; // SMCLK difference > > Oldcapture = CCR2; // Save current captured SMCLK > > > > /* if equal, leave "while(1)" */ > > if (delta == Compare) > > { > > break; > > } > > /* DCO is too fast, slow it down */ > > else if (delta < Compare) > > { > > DCOCTL--; > > /* Did DCO role under? */ > > if (DCOCTL == 0xFF) > > { > > /* Select next lower RSEL */ > > BCSCTL1--; > > } > > } > > else > > { > > DCOCTL++; > > /* Did DCO role over? */ > > if (DCOCTL == 0x00) > > { > > /* Select next higher RSEL*/ > > BCSCTL1++; > > } > > > > } > > } > > /* Stop CCR2 function */ > > CCTL2 = 0; > > /* Stop Timer_A */ > > TACTL = 0; > >} > > > >Any help will be nice > > > >best regards. > > > > > > > > > > > > > ------------------------------------------------------- > This SF.net email is sponsored by: IBM Linux Tutorials. > Become an expert in LINUX or just sharpen your skills. Sign up for IBM's > Free Linux Tutorials. Learn everything from the bash shell to sys admin. > Click now! http://ads.osdn.com/?ad_id=1278&alloc_id=3371&op=click
