Delbert Martin wrote:
> On Thu, 15 Jul 2004 13:10:20 -0500 "Garst R. Reese" <gar...@isn.net>
> wrote:
>>> I have a problem the the msp430-gcc when compiling assembly. Im
>>> using gcc-3.2.2 with msp430 Ext from the mspgcc/files on Source
>>> Forge gdb-5.1.1 with msp430 Ext from the mspgcc/files on Source
>>> Forge binutils-2.14 Note: I tried binutils-2.15 but it failed to
>>> compile/assembled gcc so I downgraded to 2.14 that seemed to
>>> work. msp430-libc
>>>
>>> im my code I add .section .vectors and describe what all of the
>>> interrupt vectors are by using .org and .word
>>>
>>
>> Sounds comlicated and error prone. Why not just:
>> interrupt(ADC_VECTOR) adc12Isr(void){ blah } or the like?
>>
I am writing most of my code in assembly. So I don't think I have the
option of using a snippet that looks like that.
yes you have, if you let the preprocessor work on your file (i.e. name
it xx.S and feed it to GCC). include signal.h, and give it a
-D_GNU_ASSEMBLER_ on the command line, so that this token is defined
when parsing the include.
the uart_test example uses asm interrupts defined that way. look at
asmlib.S in there.
> Its a pretty simple
process, you have .section .vectors which will put your code at Mem
Addr 0xFFE0 then you add the offset of your interrupt with a .org
then you use .word to insert the memory address of you ISR.
you don't show code so it's hard to tell what could have went wrong. are
you sure that you're using .org as it's intended?
I should mention I made a makefile from the msp430/Examples, I used
the assembler files there to base my assembler code on. All of the
examples are also missing their Interrupt vectors as well.
uhm, which examples? there are some from us and some converted from TI's
application notes.
if had a quick look at slac010/fet110_ta01.S which uses .org/.word style
to register interrupts. when i disassemble the binary it looks fine:
$ msp430-objdump -D fet110_ta01
fet110_ta01: file format elf32-msp430
Disassembly of section .text:
0000f000 <__ctors_end>:
f000: 31 40 00 03 mov #768, r1 ;#0x0300
0000f004 <StopWDT>:
f004: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80
f008: 20 01
0000f00a <SetupTA>:
f00a: b2 40 04 02 mov #516, &0x0160 ;#0x0204
f00e: 60 01
0000f010 <SetupC0>:
f010: b2 40 10 00 mov #16, &0x0162 ;#0x0010
f014: 62 01
f016: b2 40 50 c3 mov #-15536,&0x0172 ;#0xc350
f01a: 72 01
0000f01c <SetupP1>:
f01c: d2 d3 22 00 bis.b #1, &0x0022 ;r3 As==01
f020: b2 d0 20 00 bis #32, &0x0160 ;#0x0020
f024: 60 01
f026: 32 d2 eint
0000f028 <Mainloop>:
f028: 32 d0 10 00 bis #16, r2 ;#0x0010
f02c: 03 43 nop
0000f02e <TA0_ISR>:
f02e: d2 e3 21 00 xor.b #1, &0x0021 ;r3 As==01
f032: b2 50 50 c3 add #-15536,&0x0172 ;#0xc350
f036: 72 01
f038: 00 13 reti
Disassembly of section .vectors:
0000ffe0 <_vectors_end-0x20>:
ffe0: ff ff interrupt service routine at 0xffff
ffe2: ff ff interrupt service routine at 0xffff
ffe4: ff ff interrupt service routine at 0xffff
ffe6: ff ff interrupt service routine at 0xffff
ffe8: ff ff interrupt service routine at 0xffff
ffea: ff ff interrupt service routine at 0xffff
ffec: ff ff interrupt service routine at 0xffff
ffee: ff ff interrupt service routine at 0xffff
fff0: ff ff interrupt service routine at 0xffff
fff2: 2e f0 interrupt service routine at 0xf02e
fff4: ff ff interrupt service routine at 0xffff
fff6: ff ff interrupt service routine at 0xffff
fff8: ff ff interrupt service routine at 0xffff
fffa: ff ff interrupt service routine at 0xffff
fffc: ff ff interrupt service routine at 0xffff
fffe: 00 f0 interrupt service routine at 0xf000
chris
