Hello, Could you update CVS / GIT / BZR, thank you
PS : Don't hesitate to correct the document if you found some mistakes
/* pmm.h * * mspgcc project: MSP430 device headers (MSP430F5XX) * Power Management Module and Supply Voltage Supervisor module header * * 2009-09-08 - THLN * - created * based on Texas Instruments document : "MSP430x5xx Family User's Guide - SLAU208 Revised July 2010" * */ /* Switches: __MSP430_PMM_BASE__ - define base address of PMM module (default is 0x120). */ #define PMMPW (0xA5<<8) /* PMM password. Read as 96h, Must be written as A5h */ #define PMMCOREV_0 (0<<0) /* VCORE level 0 */ #define PMMCOREV_1 (1<<0) /* VCORE level 1 */ #define PMMCOREV_2 (2<<0) /* VCORE level 2 */ #define PMMCOREV_3 (3<<0) /* VCORE level 3 */ /* PMMCTL0 16 bits */ #define PMMPW7 (1<<15) /* PMM password 7 */ #define PMMPW6 (1<<14) /* PMM password 6 */ #define PMMPW5 (1<<13) /* PMM password 5 */ #define PMMPW4 (1<<12) /* PMM password 4 */ #define PMMPW3 (1<<11) /* PMM password 3 */ #define PMMPW2 (1<<10) /* PMM password 2 */ #define PMMPW1 (1<<9) /* PMM password 1 */ #define PMMPW0 (1<<8) /* PMM password 0 */ #define PMMREGOFF (1<<4) /* Regulator off */ #define PMMSWPOR (1<<3) /* Software power-on reset */ #define PMMSWBOR (1<<2) /* Software brownout reset. */ #define PMMCOREV1 (1<<1) /* Core voltage 1 */ #define PMMCOREV0 (1<<0) /* Core voltage 0 */ /* SVSMHCTL 16 bits */ #define SVMHFP (1<<15) /* SVM high-side full-performance mode */ #define SVMHE (1<<14) /* SVM high-side enable */ #define SVMHOVPE (1<<12) /* SVM high-side overvoltage enable */ #define SVSHFP (1<<11) /* SVS high-side full-performance mode */ #define SVSHE (1<<10) /* SVS high-side enable */ #define SVSHRVL1 (1<<9) /* SVS high-side reset voltage level 1 */ #define SVSHRVL0 (1<<8) /* SVS high-side reset voltage level 0 */ #define SVSMHACE (1<<7) /* SVS and SVM high-side automatic control enable */ #define SVSMHEVM (1<<6) /* SVS and SVM high-side event mask */ #define SVSHMD (1<<4) /* SVS high-side mode */ #define SVSMHDLYST (1<<3) /* SVS and SVM high-side delay status */ #define SVSMHRRL2 (1<<2) /* SVS and SVM high-side reset release voltage level 2 */ #define SVSMHRRL1 (1<<1) /* SVS and SVM high-side reset release voltage level 1 */ #define SVSMHRRL0 (1<<0) /* SVS and SVM high-side reset release voltage level 0 */ /* SVSMLCTL 16 bits */ #define SVMLFP (1<<15) /* SVM low-side full-performance mode */ #define SVMLE (1<<14) /* SVM low-side enable */ #define SVMLOVPE (1<<12) /* SVM low-side overvoltage enable */ #define SVSLFP (1<<11) /* SVS low-side full-performance mode */ #define SVSLE (1<<10) /* SVS low-side enable */ #define SVSLRVL1 (1<<9) /* SVS low-side reset voltage level 1 */ #define SVSLRVL0 (1<<8) /* SVS low-side reset voltage level 0 */ #define SVSMLACE (1<<7) /* SVS and SVM low-side automatic control enable. */ #define SVSMLEVM (1<<6) /* SVS and SVM low-side event mask */ #define SVSLMD (1<<4) /* SVS low-side mode */ #define SVSMLDLYST (1<<3) /* SVS and SVM low-side delay status */ #define SVSMLRRL2 (1<<2) /* SVS and SVM low-side reset release voltage level 2 */ #define SVSMLRRL1 (1<<1) /* SVS and SVM low-side reset release voltage level 1 */ #define SVSMLRRL0 (1<<0) /* SVS and SVM low-side reset release voltage level 0 */ /* SVSMIO 16 bits */ #define SVMHVLROE (1<<12) /* SVM high-side voltage level reached output enable */ #define SVMHOE (1<<11) /* SVM high-side output enable. */ #define SVMOUTPOL (1<<5) /* SVMOUT pin polarity */ #define SVMLVLROE (1<<4) /* SVM low-side voltage level reached output enable */ #define SVMLOE (1<<3) /* SVM low-side output enable */ /* PMMIFG 16 bits */ #define PMMLPM5IFG (1<<15) /* LPMx.5 flag */ #define SVSLIFG (1<<13) /* SVS low-side interrupt flag */ #define SVSHIFG (1<<12) /* SVS high-side interrupt flag */ #define PMMPORIFG (1<<10) /* PMM software power-on reset interrupt flag */ #define PMMRSTIFG (1<<9) /* PMM reset pin interrupt flag */ #define PMMBORIFG (1<<8) /* PMM software brownout reset interrupt flag */ #define SVMHVLRIFG (1<<6) /* SVM high-side voltage level reached interrupt flag */ #define SVMHIFG (1<<5) /* SVM high-side interrupt flag */ #define SVSMHDLYIFG (1<<4) /* SVS and SVM high-side delay expired interrupt flag */ #define SVMLVLRIFG (1<<2) /* SVM low-side voltage level reached interrupt flag */ #define SVMLIFG (1<<1) /* SVM low-side interrupt flag */ #define SVSMLDLYIFG (1<<0) /* SVS and SVM low-side delay expired interrupt flag */ /* PMMRIE 16 bits */ #define SVMHVLRPE (1<<13) /* SVM high-side voltage level reached power-on reset enable */ #define SVSHPE (1<<12) /* SVS high-side power-on reset enable */ #define SVMLVLRPE (1<<9) /* SVM low-side voltage level reached power-on reset enable */ #define SVSLPE (1<<8) /* SVS low-side power-on reset enable */ #define SVMHVLRIE (1<<6) /* SVM high-side reset voltage level interrupt enable */ #define SVMHIE (1<<5) /* SVM high-side interrupt enable */ #define SVSMHDLYIE (1<<4) /* SVS and SVM high-side delay expired interrupt enable */ #define SVMLVLRIE (1<<2) /* SVM low-side reset voltage level interrupt enable */ #define SVMLIE (1<<1) /* SVM low-side interrupt enable */ #define SVSMLDLYIE (1<<0) /* SVS and SVM low-side delay expired interrupt enable */ /* PM5CTL0 16 bits */ #define LOCKLPM5 (1<<0) /* Lock I/O pin configuration upon entry/exit to/from LPMx.5 */ /* PMM base address */ #if !defined(__MSP430_PMM_BASE__) #define __MSP430_PMM_BASE__ 0x120 #endif #define __MSP430_SVSM_BASE__ __MSP430_PMM_BASE__ #define __MSP430_PM5_BASE__ __MSP430_PMM_BASE__ #define PMMCTL0_ __MSP430_PMM_BASE__ + 0x0 /* PMM Control 0 Register */ sfrw(PMMCTL0, PMMCTL0_); #define PMMCTL0_L_ __MSP430_PMM_BASE__ + 0x0 /* PMM Control 0 Register Lo */ sfrb(PMMCTL0_L, PMMCTL0_L_); #define PMMCTL0_H_ __MSP430_PMM_BASE__ + 0x1 /* PMM Control 0 Register Hi */ sfrb(PMMCTL0_H, PMMCTL0_H_); #define PMMCTL1_ __MSP430_PMM_BASE__ + 0x0 /* PMM Control 1 Register */ sfrw(PMMCTL1, PMMCTL1_); #define PMMCTL1_L_ __MSP430_PMM_BASE__ + 0x0 /* PMM Control 1 Register Lo */ sfrb(PMMCTL1_L, PMMCTL1_L_); #define PMMCTL1_H_ __MSP430_PMM_BASE__ + 0x1 /* PMM Control 1 Register Hi */ sfrb(PMMCTL1_H, PMMCTL1_H_); #define PMMIFG_ __MSP430_PMM_BASE__ + 0xa /* PMM interrupt flag Register */ sfrw(PMMIFG, PMMIFG_); #define PMMIFG_L_ __MSP430_PMM_BASE__ + 0xa /* PMM interrupt flag Register Lo */ sfrb(PMMIFG_L, PMMIFG_L_); #define PMMIFG_H_ __MSP430_PMM_BASE__ + 0xb /* PMM interrupt flag Register Hi */ sfrb(PMMIFG_H, PMMIFG_H_); #define PMMRIE_ __MSP430_PMM_BASE__ + 0xe /* PMM interrupt enable Register */ sfrw(PMMRIE, PMMRIE_); #define PMMRIE_L_ __MSP430_PMM_BASE__ + 0xe /* PMM interrupt enable Register Lo */ sfrb(PMMRIE_L, PMMRIE_L_); #define PMMRIE_H_ __MSP430_PMM_BASE__ + 0xf /* PMM interrupt enable Register Hi */ sfrb(PMMRIE_H, PMMRIE_H_); #define SVSMHCTL_ __MSP430_SVSM_BASE__ + 0x4 /* SVSM SVS and SVM high side control Register */ sfrw(SVSMHCTL, SVSMHCTL_); #define SVSMHCTL_L_ __MSP430_SVSM_BASE__ + 0x4 /* SVSM SVS and SVM high side control Register Lo */ sfrb(SVSMHCTL_L, SVSMHCTL_L_); #define SVSMHCTL_H_ __MSP430_SVSM_BASE__ + 0x5 /* SVSM SVS and SVM high side control Register Hi */ sfrb(SVSMHCTL_H, SVSMHCTL_H_); #define SVSMMLCTL_ __MSP430_SVSM_BASE__ + 0x6 /* SVSM SVS and SVM low side control Register */ sfrw(SVSMMLCTL, SVSMMLCTL_); #define SVSMMLCTL_L_ __MSP430_SVSM_BASE__ + 0x6 /* SVSM SVS and SVM low side control Register Lo */ sfrb(SVSMMLCTL_L, SVSMMLCTL_L_); #define SVSMMLCTL_H_ __MSP430_SVSM_BASE__ + 0x7 /* SVSM SVS and SVM low side control Register Hi */ sfrb(SVSMMLCTL_H, SVSMMLCTL_H_); #define SVSMMLCTL_ __MSP430_SVSM_BASE__ + 0x8 /* SVSM SVSIN and SVMOUT control (optional) Register */ sfrw(SVSMMLCTL, SVSMMLCTL_); #define SVSMMLCTL_L_ __MSP430_SVSM_BASE__ + 0x8 /* SVSM SVSIN and SVMOUT control (optional) Register Lo */ sfrb(SVSMMLCTL_L, SVSMMLCTL_L_); #define SVSMMLCTL_H_ __MSP430_SVSM_BASE__ + 0x9 /* SVSM SVSIN and SVMOUT control (optional) Register Hi */ sfrb(SVSMMLCTL_H, SVSMMLCTL_H_); #define PM5CTL0_ __MSP430_PM5_BASE__ + 0x10 /* PM5 Control 0 Register */ sfrw(PM5CTL0, PM5CTL0_); #define PM5CTL0_L_ __MSP430_PM5_BASE__ + 0x10 /* PM5 Control 0 Register Lo */ sfrb(PM5CTL0_L, PM5CTL0_L_); #define PM5CTL0_H_ __MSP430_PM5_BASE__ + 0x11 /* PM5 Control 0 Register Hi */ sfrb(PM5CTL0_H, PM5CTL0_H_);
