Hello, Could you update CVS / GIT / BZR, thank you
PS : Don't hesitate to correct the document if you found some mistakes
#ifndef __MSP430_HEADERS_RTC_H #define __MSP430_HEADERS_RTC_H /* rtc.h * * mspgcc project: MSP430 device headers (MSP430F5XX) * RTC module header * * 2009-09-08 - THLN * - created * based on Texas Instruments document : "MSP430x5xx Family User's Guide - SLAU208 Revised July 2010" * */ /* Switches: __MSP430_RTC_BASE__ - define base address of RTC module (default is 0x4a0). __MSP430_HAS_RTCB__ - if rtc version B. */ /* Real-Time Clock base address */ #if !defined(__MSP430_RTC_BASE__) #define __MSP430_RTC_BASE__ 0x4a0 #endif #define RTCCTL01_ __MSP430_RTC_BASE__ + 0x0 /* Real-Time Clock Control Word 0, 1 Register */ sfrw(RTCCTL01, RTCCTL01_); #define RTCCTL01_L_ __MSP430_RTC_BASE__ + 0x0 /* Real-Time Clock Control Word 0, 1 Register Lo */ sfrb(RTCCTL01_L, RTCCTL01_L_); #define RTCCTL01_H_ __MSP430_RTC_BASE__ + 0x1 /* Real-Time Clock Control Word 0, 1 Register Hi */ sfrb(RTCCTL01_H, RTCCTL01_H_); #define RTCCTL0_ __MSP430_RTC_BASE__ + 0x0 /* Real-Time Clock Control 0 Register */ sfrb(RTCCTL0, RTCCTL0_); #define RTCCTL1_ __MSP430_RTC_BASE__ + 0x1 /* Real-Time Clock Control 1 Register */ sfrb(RTCCTL1, RTCCTL1_); #define RTCCTL23_ __MSP430_RTC_BASE__ + 0x2 /* Real-Time Clock Control Word 2, 3 Register */ sfrw(RTCCTL23, RTCCTL23_); #define RTCCTL23_L_ __MSP430_RTC_BASE__ + 0x2 /* Real-Time Clock Control Word 2, 3 Register Lo */ sfrb(RTCCTL23_L, RTCCTL23_L_); #define RTCCTL23_H_ __MSP430_RTC_BASE__ + 0x3 /* Real-Time Clock Control Word 2, 3 Register Hi */ sfrb(RTCCTL23_H, RTCCTL23_H_); #define RTCCTL2_ __MSP430_RTC_BASE__ + 0x2 /* Real-Time Clock Control 2 Register */ sfrb(RTCCTL2, RTCCTL2_); #define RTCCTL3_ __MSP430_RTC_BASE__ + 0x3 /* Real-Time Clock Control 3 Register */ sfrb(RTCCTL3, RTCCTL3_); #define RTCPS0CTL_ __MSP430_RTC_BASE__ + 0x8 /* Real-Time Clock Prescale Timer 0 Control Register */ sfrw(RTCPS0CTL, RTCPS0CTL_); #define RTCPS0CTL_L_ __MSP430_RTC_BASE__ + 0x8 /* Real-Time Clock Prescale Timer 0 Control Register Lo */ sfrb(RTCPS0CTL_L, RTCPS0CTL_L_); #define RTCPS0CTL_H_ __MSP430_RTC_BASE__ + 0x9 /* Real-Time Clock Prescale Timer 0 Control Register Hi */ sfrb(RTCPS0CTL_H, RTCPS0CTL_H_); #define RTCPS1CTL_ __MSP430_RTC_BASE__ + 0xa /* Real-Time Clock Prescale Timer 1 Control Register */ sfrw(RTCPS1CTL, RTCPS1CTL_); #define RTCPS1CTL_L_ __MSP430_RTC_BASE__ + 0xa /* Real-Time Clock Prescale Timer 1 Control Register Lo */ sfrb(RTCPS1CTL_L, RTCPS1CTL_L_); #define RTCPS1CTL_H_ __MSP430_RTC_BASE__ + 0xb /* Real-Time Clock Prescale Timer 1 Control Register Hi */ sfrb(RTCPS1CTL_H, RTCPS1CTL_H_); #define RTCPS_ __MSP430_RTC_BASE__ + 0xc /* Real-Time Clock Prescale Timer 0, 1 Counter Register */ sfrw(RTCPS, RTCPS_); #define RTCPS_L_ __MSP430_RTC_BASE__ + 0xc /* Real-Time Clock Prescale Timer 0, 1 Counter Register Lo */ sfrb(RTCPS_L, RTCPS_L_); #define RTCPS_H_ __MSP430_RTC_BASE__ + 0xd /* Real-Time Clock Prescale Timer 0, 1 Counter Register Hi */ sfrb(RTCPS_H, RTCPS_H_); #define RTC0PS_ __MSP430_RTC_BASE__ + 0xc /* Real-Time Clock Prescale Timer 0 Counter Register */ sfrb(RTC0PS, RTC0PS_); #define RTC1PS_ __MSP430_RTC_BASE__ + 0xd /* Real-Time Clock Prescale Timer 1 Counter Register */ sfrb(RTC1PS, RTC1PS_); #define RTCIV_ __MSP430_RTC_BASE__ + 0xe /* Real-Time Clock Interrupt Vector Register */ sfrw(RTCIV, RTCIV_); #define RTCIV_L_ __MSP430_RTC_BASE__ + 0xe /* Real-Time Clock Interrupt Vector Register Lo */ sfrb(RTCIV_L, RTCIV_L_); #define RTCIV_H_ __MSP430_RTC_BASE__ + 0xf /* Real-Time Clock Interrupt Vector Register Hi */ sfrb(RTCIV_H, RTCIV_H_); #define RTCTIM0_ __MSP430_RTC_BASE__ + 0x10 /* Real-Time Clock Seconds, Minutes Register */ sfrw(RTCTIM0, RTCTIM0_); #define RTCTIM0_L_ __MSP430_RTC_BASE__ + 0x10 /* Real-Time Clock Seconds, Minutes Register Lo */ sfrb(RTCTIM0_L, RTCTIM0_L_); #define RTCTIM0_H_ __MSP430_RTC_BASE__ + 0x11 /* Real-Time Clock Seconds, Minutes Register Hi */ sfrb(RTCTIM0_H, RTCTIM0_H_); #define RTCNT12_ __MSP430_RTC_BASE__ + 0x10 /* Real-Time Clock Counter 1, 2 Register */ sfrw(RTCNT12, RTCNT12_); #define RTCNT12_L_ __MSP430_RTC_BASE__ + 0x10 /* Real-Time Clock Counter 1, 2 Register Lo */ sfrb(RTCNT12_L, RTCNT12_L_); #define RTCNT12_H_ __MSP430_RTC_BASE__ + 0x11 /* Real-Time Clock Counter 1, 2 Register Hi */ sfrb(RTCNT12_H, RTCNT12_H_); #define RTCSEC_ __MSP430_RTC_BASE__ + 0x10 /* Real-Time Clock Clock Seconds Register */ sfrb(RTCSEC, RTCSEC_); #define RTCNT1_ __MSP430_RTC_BASE__ + 0x10 /* Real-Time Clock Counter 1 Register */ sfrb(RTCNT1, RTCNT1_); #define RTCMIN_ __MSP430_RTC_BASE__ + 0x11 /* Real-Time Clock Minutes Register */ sfrb(RTCMIN, RTCMIN_); #define RTCNT2_ __MSP430_RTC_BASE__ + 0x11 /* Real-Time Clock Counter 2 Register */ sfrb(RTCNT2, RTCNT2_); #define RTCTIM1_ __MSP430_RTC_BASE__ + 0x12 /* Real-Time Clock Hour, Day of Week Register */ sfrw(RTCTIM1, RTCTIM1_); #define RTCTIM1_L_ __MSP430_RTC_BASE__ + 0x12 /* Real-Time Clock Hour, Day of Week Register Lo */ sfrb(RTCTIM1_L, RTCTIM1_L_); #define RTCTIM1_H_ __MSP430_RTC_BASE__ + 0x13 /* Real-Time Clock Hour, Day of Week Register Hi */ sfrb(RTCTIM1_H, RTCTIM1_H_); #define RTCNT23_ __MSP430_RTC_BASE__ + 0x12 /* Real-Time Clock Counter 3, 4 Register */ sfrw(RTCNT23, RTCNT23_); #define RTCNT23_L_ __MSP430_RTC_BASE__ + 0x12 /* Real-Time Clock Counter 3, 4 Register Lo */ sfrb(RTCNT23_L, RTCNT23_L_); #define RTCNT23_H_ __MSP430_RTC_BASE__ + 0x13 /* Real-Time Clock Counter 3, 4 Register Hi */ sfrb(RTCNT23_H, RTCNT23_H_); #define RTCHOUR_ __MSP430_RTC_BASE__ + 0x12 /* Real-Time Clock Hour Register */ sfrb(RTCHOUR, RTCHOUR_); #define RTCNT3_ __MSP430_RTC_BASE__ + 0x12 /* Real-Time Clock Counter 3 Register */ sfrb(RTCNT3, RTCNT3_); #define RTCMIN_ __MSP430_RTC_BASE__ + 0x13 /* Real-Time Clock Day of Week Register */ sfrb(RTCMIN, RTCMIN_); #define RTCNT4_ __MSP430_RTC_BASE__ + 0x13 /* Real-Time Clock Counter 4 Register */ sfrb(RTCNT4, RTCNT4_); #define RTCDATE_ __MSP430_RTC_BASE__ + 0x14 /* Real-Time Clock Date Register */ sfrw(RTCDATE, RTCDATE_); #define RTCDATE_L_ __MSP430_RTC_BASE__ + 0x14 /* Real-Time Clock Date Register Lo */ sfrb(RTCDATE_L, RTCDATE_L_); #define RTCDATE_H_ __MSP430_RTC_BASE__ + 0x15 /* Real-Time Clock Date Register Hi */ sfrb(RTCDATE_H, RTCDATE_H_); #define RTCDAY_ __MSP430_RTC_BASE__ + 0x14 /* Real-Time Clock Day of Month Register */ sfrb(RTCDAY, RTCDAY_); #define RTCMON_ __MSP430_RTC_BASE__ + 0x15 /* Real-Time Clock Month Register */ sfrb(RTCMON, RTCMON_); #define RTCYEAR_ __MSP430_RTC_BASE__ + 0x16 /* Real-Time Clock Year Register */ sfrw(RTCYEAR, RTCYEAR_); #define RTCYEAR_L_ __MSP430_RTC_BASE__ + 0x16 /* Real-Time Clock Year Register Lo */ sfrb(RTCYEAR_L, RTCYEAR_L_); #define RTCYEAR_H_ __MSP430_RTC_BASE__ + 0x17 /* Real-Time Clock Year Register Hi */ sfrb(RTCYEAR_H, RTCYEAR_H_); #define RTCAMINHR_ __MSP430_RTC_BASE__ + 0x18 /* Real-Time Clock Minutes, Hour Alarm Register */ sfrw(RTCAMINHR, RTCAMINHR_); #define RTCAMINHR_L_ __MSP430_RTC_BASE__ + 0x18 /* Real-Time Clock Minutes, Hour Alarm Register Lo */ sfrb(RTCAMINHR_L, RTCAMINHR_L_); #define RTCAMINHR_H_ __MSP430_RTC_BASE__ + 0x19 /* Real-Time Clock Minutes, Hour Alarm Register Hi */ sfrb(RTCAMINHR_H, RTCAMINHR_H_); #define RTCAMIN_ __MSP430_RTC_BASE__ + 0x18 /* Real-Time Clock Minutes Alarm Register */ sfrb(RTCAMIN, RTCAMIN_); #define RTCAHOUR_ __MSP430_RTC_BASE__ + 0x19 /* Real-Time Clock Hour Alarm Register */ sfrb(RTCAHOUR, RTCAHOUR_); #define RTCADOWDAY_ __MSP430_RTC_BASE__ + 0x1a /* Real-Time Clock Day of Week, Day of Month Alarm Register */ sfrw(RTCADOWDAY, RTCADOWDAY_); #define RTCADOWDAY_L_ __MSP430_RTC_BASE__ + 0x1a /* Real-Time Clock Day of Week, Day of Month Alarm Register Lo */ sfrb(RTCADOWDAY_L, RTCADOWDAY_L_); #define RTCADOWDAY_H_ __MSP430_RTC_BASE__ + 0x1b /* Real-Time Clock Day of Week, Day of Month Alarm Register Hi */ sfrb(RTCADOWDAY_H, RTCADOWDAY_H_); #define RTCADOW_ __MSP430_RTC_BASE__ + 0x1a /* Real-Time Clock Day of Week Alarm Register */ sfrb(RTCADOW, RTCADOW_); #define RTCADAY_ __MSP430_RTC_BASE__ + 0x1b /* Real-Time Clock Day of Month Alarm Register */ sfrb(RTCADAY, RTCADAY_); #if defined(__MSP430_HAS_RTCB__) #define BIN2BCD_ __MSP430_RTC_BASE__ + 0x1c /* Real-Time Clock Binary-to-BCD conversion register Register */ sfrw(BIN2BCD, BIN2BCD_); #define BIN2BCD_L_ __MSP430_RTC_BASE__ + 0x1c /* Real-Time Clock Binary-to-BCD conversion register Register Lo */ sfrb(BIN2BCD_L, BIN2BCD_L_); #define BIN2BCD_H_ __MSP430_RTC_BASE__ + 0x1d /* Real-Time Clock Binary-to-BCD conversion register Register Hi */ sfrb(BIN2BCD_H, BIN2BCD_H_); #define BCD2BIN_ __MSP430_RTC_BASE__ + 0x1e /* Real-Time Clock BCD-to-binary conversion register Register */ sfrw(BCD2BIN, BCD2BIN_); #define BCD2BIN_L_ __MSP430_RTC_BASE__ + 0x1e /* Real-Time Clock BCD-to-binary conversion register Register Lo */ sfrb(BCD2BIN_L, BCD2BIN_L_); #define BCD2BIN_H_ __MSP430_RTC_BASE__ + 0x1f /* Real-Time Clock BCD-to-binary conversion register Register Hi */ sfrb(BCD2BIN_H, BCD2BIN_H_); #endif /* __MSP430_HAS_RTCB__ */ /* RTCCTL01 16 bits */ #define RTCBCD (1<<15) /* RTC BCD 0:Binary / 1:BCD */ #define RTCHOLD (1<<14) /* RTC Hold */ #define RTCMODE (1<<13) /* RTC Mode 0:Counter / 1: Calendar */ #define RTCRDY (1<<12) /* RTC Ready */ #define RTCSSEL1 (1<<11) /* RTC Source Select 1 */ #define RTCSSEL0 (1<<10) /* RTC Source Select 0 */ #define RTCTEV1 (1<<9) /* RTC Time Event 1 */ #define RTCTEV0 (1<<8) /* RTC Time Event 0 */ #define RTCTEVIE (1<<6) /* RTC Time Event Interrupt Enable Flag */ #define RTCAIE (1<<5) /* RTC Alarm Interrupt Enable Flag */ #define RTCRDYIE (1<<4) /* RTC Ready Interrupt Enable Flag */ #define RTCTEVIFG (1<<2) /* RTC Time Event Interrupt Flag */ #define RTCAIFG (1<<1) /* RTC Alarm Interrupt Flag */ #define RTCRDYIFG (1<<0) /* RTC Ready Interrupt Flag */ /* RTCCTL01 8H+8L bits */ #define RTCBCD_H (1<<7) /* RTC BCD 0:Binary / 1:BCD */ #define RTCHOLD_H (1<<6) /* RTC Hold */ #define RTCMODE_H (1<<5) /* RTC Mode 0:Counter / 1: Calendar */ #define RTCRDY_H (1<<4) /* RTC Ready */ #define RTCSSEL1_H (1<<3) /* RTC Source Select 1 */ #define RTCSSEL0_H (1<<2) /* RTC Source Select 0 */ #define RTCTEV1_H (1<<1) /* RTC Time Event 1 */ #define RTCTEV0_H (1<<0) /* RTC Time Event 0 */ #define RTCTEVIE_L (1<<6) /* RTC Time Event Interrupt Enable Flag */ #define RTCAIE_L (1<<5) /* RTC Alarm Interrupt Enable Flag */ #define RTCRDYIE_L (1<<4) /* RTC Ready Interrupt Enable Flag */ #define RTCTEVIFG_L (1<<2) /* RTC Time Event Interrupt Flag */ #define RTCAIFG_L (1<<1) /* RTC Alarm Interrupt Flag */ #define RTCRDYIFG_L (1<<0) /* RTC Ready Interrupt Flag */ /* RTCCTL23 16 bits */ #define RTCCALF1 (1<<9) /* RTC Calibration Frequency Bit 1 */ #define RTCCALF0 (1<<8) /* RTC Calibration Frequency Bit 0 */ #define RTCCALS (1<<7) /* RTC Calibration Sign */ #define RTCCAL5 (1<<5) /* RTC Calibration Bit 5 */ #define RTCCAL4 (1<<4) /* RTC Calibration Bit 4 */ #define RTCCAL3 (1<<3) /* RTC Calibration Bit 3 */ #define RTCCAL2 (1<<2) /* RTC Calibration Bit 2 */ #define RTCCAL1 (1<<1) /* RTC Calibration Bit 1 */ #define RTCCAL0 (1<<0) /* RTC Calibration Bit 0 */ /* RTCCTL23 8H+8L bits */ #define RTCCALF1_H (1<<1) /* RTC Calibration Frequency Bit 1 */ #define RTCCALF0_H (1<<0) /* RTC Calibration Frequency Bit 0 */ #define RTCCALS_L (1<<7) /* RTC Calibration Sign */ #define RTCCAL5_L (1<<5) /* RTC Calibration Bit 5 */ #define RTCCAL4_L (1<<4) /* RTC Calibration Bit 4 */ #define RTCCAL3_L (1<<3) /* RTC Calibration Bit 3 */ #define RTCCAL2_L (1<<2) /* RTC Calibration Bit 2 */ #define RTCCAL1_L (1<<1) /* RTC Calibration Bit 1 */ #define RTCCAL0_L (1<<0) /* RTC Calibration Bit 0 */ /* RTCPS0CTL 16 bits */ #define RT0SSEL (1<<14) /* RTC Prescale timer 0 clock source select */ #define RT0PSDIV2 (1<<13) /* RTC Prescale timer 0 clock divide 2 */ #define RT0PSDIV1 (1<<12) /* RTC Prescale timer 0 clock divide 1 */ #define RT0PSDIV0 (1<<11) /* RTC Prescale timer 0 clock divide 0 */ #define RT0PSHOLD (1<<8) /* RTC Prescale timer 0 hold */ #define RT0IP_2 (1<<4) /* RTC Prescale timer 0 interrupt interval 2 */ #define RT0IP_1 (1<<3) /* RTC Prescale timer 0 interrupt interval 1 */ #define RT0IP_0 (1<<2) /* RTC Prescale timer 0 interrupt interval 0 */ #define RT0PSIE (1<<1) /* RTC Prescale timer 0 interrupt enable */ #define RT0PSIFG (1<<0) /* RTC Prescale timer 0 interrupt flag */ /* RTCPS0CTL 8H+8L bits */ #define RT0SSEL_H (1<<6) /* RTC Prescale timer 0 clock source select */ #define RT0PSDIV2_H (1<<5) /* RTC Prescale timer 0 clock divide 2 */ #define RT0PSDIV1_H (1<<4) /* RTC Prescale timer 0 clock divide 1 */ #define RT0PSDIV0_H (1<<3) /* RTC Prescale timer 0 clock divide 0 */ #define RT0PSHOLD_H (1<<0) /* RTC Prescale timer 0 hold */ #define RT0IP_2_L (1<<4) /* RTC Prescale timer 0 interrupt interval 2 */ #define RT0IP_1_L (1<<3) /* RTC Prescale timer 0 interrupt interval 1 */ #define RT0IP_0_L (1<<2) /* RTC Prescale timer 0 interrupt interval 0 */ #define RT0PSIE_L (1<<1) /* RTC Prescale timer 0 interrupt enable */ #define RT0PSIFG_L (1<<0) /* RTC Prescale timer 0 interrupt flag */ /* RTCPS1CTL 16 bits */ #define RT1SSEL1 (1<<15) /* RTC Prescale timer 1 clock source select 1 */ #define RT1SSEL0 (1<<14) /* RTC Prescale timer 1 clock source select 0 */ #define RT1PSDIV2 (1<<13) /* Prescale timer 1 clock divide 2 */ #define RT1PSDIV1 (1<<12) /* Prescale timer 1 clock divide 1 */ #define RT1PSDIV0 (1<<11) /* Prescale timer 1 clock divide 0 */ #define RT1PSHOLD (1<<8) /* RTC Prescale timer 1 hold */ #define RT1IP_2 (1<<4) /* RTC Prescale timer 1 interrupt interval 2 */ #define RT1IP_1 (1<<3) /* RTC Prescale timer 1 interrupt interval 1 */ #define RT1IP_0 (1<<2) /* RTC Prescale timer 1 interrupt interval 0 */ #define RT1PSIE (1<<1) /* RTC Prescale timer 1 interrupt enable */ #define RT1PSIFG (1<<0) /* RTC Prescale timer 1 interrupt flag */ /* RTCPS1CTL 8H+8L bits */ #define RT1SSEL1_H (1<<7) /* RTC Prescale timer 1 clock source select 1 */ #define RT1SSEL0_H (1<<6) /* RTC Prescale timer 1 clock source select 0 */ #define RT1PSDIV2_H (1<<5) /* Prescale timer 1 clock divide 2 */ #define RT1PSDIV1_H (1<<4) /* Prescale timer 1 clock divide 1 */ #define RT1PSDIV0_H (1<<3) /* Prescale timer 1 clock divide 0 */ #define RT1PSHOLD_H (1<<0) /* RTC Prescale timer 1 hold */ #define RT1IP_2_L (1<<4) /* RTC Prescale timer 1 interrupt interval 2 */ #define RT1IP_1_L (1<<3) /* RTC Prescale timer 1 interrupt interval 1 */ #define RT1IP_0_L (1<<2) /* RTC Prescale timer 1 interrupt interval 0 */ #define RT1PSIE_L (1<<1) /* RTC Prescale timer 1 interrupt enable */ #define RT1PSIFG_L (1<<0) /* RTC Prescale timer 1 interrupt flag */ #endif /* __MSP430_HEADERS_RTC_H */
