>] >> > RRCA ; 5 clocks
>]
>] Hey RRCA takes (just like RLCA) 4 T-states, doesn't it?
>Laurens,
>
>As somebody already mentioned:
>You have to add one T-state to it in the MSX system. The additional T-state
>is needed because the MSX inserts one wait state in the M1 cycle. This wait
>state is intended to give the memory refresh circuit time to refresh the
>correct row of memory. Something which was still needed back in '83,'84
when
>SVI and ASCII designed the MSX system.
>
>Unfortunately, this wait state can't be removed anymore now that the memory
>has become fast enough. Removing the wait state would influence the timing
of
>some programs too much. For example sample replayers on the Z80 use the
exact
>MSX timing to be able to play samples at the correct samplerate.
Drat!
Then all my calculations I have made till now are wrong!
But... a LD A,(DE) is now 2 T-states faster than 2 NOPs!!! Yess!!!
Would this single state differ that much??? It will speed up things alot I
think but the VDP can handle 1 T-state less I think. Music Module probably
can handle it at 3.5MHz, probably not on 7MHz (it already has timing
problems now), but I'm not gonna use my music-module on 7MHz anyway. Vive la
MoonSound.
Is this easy to do, removing this extra T-state???
~Grauw
>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<
Email me: [EMAIL PROTECTED]
Visit my (Grauw & Datax') homepage at
http://datax.cjb.net/ ... Live long and prosper
>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<
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