Yo guys.
I know how the hardware behind a standard MSX slot expander works ...
> In order to be a expanded MSX slot, you would have to catch writes to
> the address FFFFh, or -1, and use this information (per 16K block) together
> with adresslines A0..A13, to enable the subslots.
Well It's almost 100% right. We use from A0 to A15 NANDed
to decode $FFFF from any slot. Then we OR the $FFFF output
with the /SLOTSEL from the slot wanted to be expanded.
The page switching effect is achieved using an 74ls153 (dual FOUR to
ONE
multplexer) tied up to A14 and A15 together with an half part of 74LS139
(Dual 2 to 4 demultiplexer) on 74ls139 outputs we do have the secondary
slots.
There's the block diagram for it :
|-------------|
A0-A15 =>|ADDR Decoder |---|
SLTSEL =>|-------------| |
| |
| |-------------| |---------------|
| D0-D7 =>|8bit Register| = | Inverter latch| => D0-D7
| Reset =>|-------------| | |---------------|
| |
| |-------| |=|---------| |------| SlotX-0
------|exclude| A14-15=> | 74ls153 |---| 74ls | SlotX-1
|logic | |---------|---| 139 | SlotX-2
|-------|----------------------------|------| SlotX-3
^ This signal is /SLOTSEL less $FFFF address,
to void conflict between devices connected to secondary slots and the
slot expander register. Some european slotexpanders doesn't seem to
implement this , making them unusable to connect external memory
mappers.
Here's a brief explanation of this block diagram.
The ADDR decoder consists of a big NAND port with 16 inputs or a
equivalent digital
circuit.
It also decodes read or write cycles , enabling the 8-bit register for
write cycles
and inverter latch for read cycles.
The 8 bit register is who you're writing to when twitting to when do the
famous "poke -1,170"
It's function is holding the active secondary slots active for each one
of the system address area
pages. This register value SHOULD be 0 when issued a RESET signal.
That's why it takes a /Reset signal
from the system.
The meaning of each pair of bits is well known by almost each msx
programmer in this mailing
list , so then I'm not going to explain here. This part of the slot
expander outputs directly to
the 74LS153 chip.
This circuit is enabled by ADDR Decoder + /WR signal.
The inverter latch is the block which gives the inverted byte when you
read from $FFFF at an expanded
primary slot. This circuit is enabled by the ADDR decoder + /RD signal.
74LS153 is the block of the slot expander that actually do the hard part
of the decoding work
from A14-A15 regarding the output of the 8bit register. This block
together with the 74LS139
do outputs the expanded slot enable signals.
Exclude logic fits on the purpose of excluding the physical address of
the slot expander register
on the secondary slots, avoiding conflicts with devices that use the
page 3 of their slots.
Since megaroms , floppy drive interfaces and almost all MSX cartridges
don't uses the page 3
then it will be not easy to figure out if your MSX Slot expander is
correctly built. I already
had a petry slot expander, and it DO had this problem. That made it
unusable to connecting
memory mappers and stuff like.
If the interested people want a schematic of this slot expander
(simplified version , inspired
on ASCII design at MSX Datapack) I can make it available in GIF or JPG
format.
Cya MSXers ...
****
MSX Mailinglist. To unsubscribe, send an email to [EMAIL PROTECTED]
and put "unsubscribe msx [EMAIL PROTECTED]" (without the quotes) in
the body (not the subject) of the message.
Problems? contact [EMAIL PROTECTED]
More information on MSX can be found in the following places:
The MSX faq: http://www.faq.msxnet.org/
The MSX newsgroup: comp.sys.msx
The MSX IRC channel: #MSX on Undernet
****
