On Wed, 26 Apr 2000 01:06:05 +0000, Maarten ter Huurne wrote:
>"Not all Z80 interrupt modes are supported. The AB180-20 uses interrupt
>mode 2 only. The interrupt mode instructions are treated as NOPs. Z80
>interrupt acknowledge cycles are not generated."
>In the chapter out interrupts things become a bit clearer.
>If I interpreted it correctly, it's like this:
>- INT0 always causes a jump to #0038 (IM1 behaviour)
>- INT1 and INT2 use a vector mechanism, but not like IM2:
> they use a 32-byte there the mapping from interrupt source to
> table index is fixed and not specified on the bus like IM2
>For MSX this means that IM2 is not available. Neither is IM0, but that
>was unused anyway.
There is no problem, I think. MSX standard is about IM1, right?
>Another incompatiblity with Z80:
>"The Z80 has some undocumented instructions, such as being able to load the
>upper or lower 8 bits of the index register (IY and IX) independently.
>This was used by a handful of programs, especially some "copy protected"
>code. The AB180-20 does not support all of the undocumented Z80
>instructions."
>But Z180 doesn't have IXH/IXL instructions either, right?
Yes, but Z180 has trap... the AB180 has trap feature?
>This may be a serious one:
>"The on-chip register addresses are located in the I/O address space from
>0000H to 00FFH (16-bit I/O addresses). In order to access the on-chip I/O
>registers (using I/O instruction), the high-order 8 bits of the 16-bit I/O
>address must be 0."
>This means the MSX I/O ports will be inaccessable if the high-order 8 bits
>happen to be zero. Those high-order bits come from one of the registers,
>right? I thought it was B, but Laurens said A. Anyway, the value of that
>register is unknown in MSX programs.
I think this can be solved by hardware (add something to "trash" the upper
8 bits always they are 0x00... (-;
>By the way, the DMA on this processor looks real cool. It can also perform
>DMA from memory to I/O and vice versa. It could be used for example to
>upload samples to the MoonSound or Music Module.
I'm waiting Ademir's answer. I talk to him by phone and he liked a lot
of the 20MIPS at 20Mhz idea... (-; Also, the chip supporst a 40Mhz bus,
also, if needed, as he said.
Abra�OS/2, Daniel Caetano ([EMAIL PROTECTED])
...!m.tag
OS/2 Sites: http://www.quasarbbs.com/daniel/
http://www.geocities.com/SiliconValley/8752/os2hp/os2index.html
MSX Sites: http://www.fudeba.cjb.net/
Drawings: http://www.djgallery.tsx.org/
****
MSX Mailinglist. To unsubscribe, send an email to [EMAIL PROTECTED]
and put "unsubscribe msx [EMAIL PROTECTED]" (without the quotes) in
the body (not the subject) of the message.
Problems? contact [EMAIL PROTECTED]
More information on MSX can be found in the following places:
The MSX faq: http://www.faq.msxnet.org/
The MSX newsgroup: comp.sys.msx
The MSX IRC channel: #MSX on Undernet
****
