On Sun, Dec 10, 2000 at 05:54:04PM +0000, Maarten ter Huurne wrote:
> Both SCREEN7 and SCREEN8 are only available on machines with 128K VRAM. That
> 128K VRAM is devided over 2 64K RAM ICs. To get the most speed out of the
> RAM, both ICs are addressed alternatingly (that's my theory anyway).
>
> Every even pixel in SCREEN7/8 is located in the first IC, that is the first
> 64K of VRAM. Every odd pixel is located in the second IC, the second 64K of
> VRAM.
>
> Note that SCREEN10/11/12 are actually SCREEN8 with YJK conversion enabled.
> They use the same VRAM mapping as SCREEN8.
>
> So in SCREEN8 the formula to get the address of a pixel is:
> (taken from modified V9938.c)
> #define VDP_VRMP8(X, Y) (VRAM + ((X&1)<<16) + ((Y&511)<<7) + ((X&255)>>1))
So when OUT (#98) is done the address latch is remapped like:
remapped = ((address&1)<<16)|(address>>1);
Correct?
> And in SCREEN7 the formula is:
> #define VDP_VRMP7(X, Y) (VRAM + ((X&1)<<16) + ((Y&511)<<7) + ((X&511)>>2))
>
> However, the VDP acts as if the VRAM is stored as one single area. So the
> programmer almost never notices this mapping. But when you switch screen
> modes and you continue to use the VRAM contents under a different mapping,
> you will have to take care of the mapping.
>
> For example, Laydock 2 Last Attack loads SCREEN5 graphics while displaying
> its SCREEN12 title image. Without the reorder code, part of the intro demo
> animation is garbage.
>
> SCREEN7 reorder is more difficult to implement than SCREEN8, because what
> appears to be a byte to the programmer is actually spread over two VRAM
> locations. For example, when a byte is written through port #98, it must be
> split into two nibbles which end up in different VRAM locations.
In the define above, (X&2) is unused; I assume this determines whether the
high or the low nibble is used. Probably if (X&2) is set, it is the low
nibble (bit 3 - bit 0) and if it's not set, it's the high nibble (bit 7 - bit 4).
Is that correct Maarten?
Sean
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