Can you say more, please? I've never understood raw.
For example:-
If application talks to a reader setting RAW mode, it is
telling the device to simply clock out the bits (and thus
not bother with T0, T1, etc)
Assuming that, what I never understand is: who is
responsible
for I2C framing and signaling (if I2C is the std)?
Is it the reader device's port (verilog behind custom I2C
registers),
or it some IFD drivers?
Things are not even just limited to the framing/acks. Every
sync devices seems to have its own reset conditions, which
implies that the IFD needs to be in control of this pin,
remotely. So, is SCARD_PROTOCOL_RAW a signal to the IFD?
Ill send folks sync cards that come with a French 4bit sync
cipher in hardlogic, if anyone wants to play and then
publish.
There would be some NDA rules, to observe formally, to
protect
the manufacturer. But it would be interesting to play with
it
all at 1.5Mbps, in a $1 (packaged) chip, with tiny power
consumption.
Talking of coding, Happy MMVII!
----- Original Message -----
From: "Ludovic Rousseau" <[EMAIL PROTECTED]>
To: "MUSCLE" <[email protected]>
Sent: Sunday, December 31, 2006 5:44 AM
Subject: Re: [Muscle] Card not transacted: 612 (drives me
nuts)
On 28/12/06, Robert Nagy <[EMAIL PROTECTED]> wrote:
Because these cards cannot be read with T=1 or T=0.
As i know the card I use (which is SLE 4442) is a
synchronous card
which can be read by the raw protocol.
Am i wrong?
If your CASTLES EZ100PU reader supports synchronous cards
and your
driver supports SCARD_PROTOCOL_RAW that should work.
But PC/SC (and pcsc-lite) does not support synchronous
cards.
It should be supported with PC/SC v2 but pcsc-lite does
not support
this API version yet.
Bye,
--
Dr. Ludovic Rousseau
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