Years ago I attended a talk on Chebyshev polynomials and someone asked if they could be used to approximate trig functions. My memory is hazy at best, but here's what I recall: the answer was something like "you could, but it would be very slow, so in practice I think that would be a bad idea". Someone else said that the CORDIC algorithm is what's used in pocket calculators for approximating trig functions. I remember hm going on to say something like "Unfortunately, the CORDIC algorithm is mind-numbingly boring and Chebychev polynomials are really interesting".
Well, to each his own. Perhaps you'll enjoy CORDIC: https://en.wikipedia.org/wiki/CORDIC On Tue, Jan 19, 2016 at 1:56 PM, Alan Wolfe <alan.wo...@gmail.com> wrote: > Chebyshev is indeed a decent way to approximate trig from what I've read. ( > http://www.embeddedrelated.com/showarticle/152.php) > > Did you know that rational quadratic Bezier curves can exactly represent > conic sections, and thus give you exact trig values? You essentially > divide one quadratic Bezier curve by another, with specifically calculated > weights. Fairly simple and straightforward stuff. Not sure if the > division is a problem for you mapping it to circuitry. > http://demofox.org/bezquadrational.html > > Video cards use a handful of terms of taylor series, so that might be a > decent approach as well since it's used in high end production circuitry. > > > On Tue, Jan 19, 2016 at 10:05 AM, Theo Verelst <theo...@theover.org> > wrote: > >> Hi all, >> >> Maybe a bit forward, but hey, there are PhDs here, too, so here it goes: >> I've played a little with the latest Vivado HLx design tools fro Xilinx >> FPGAs and the cheap Zynq implementation I use (a Parallella board), and I >> was looking for interesting examples to put in C-to_chip compiler that I >> can connected over AXI bus to a Linux program running on the ARM cores in >> the Zynq chip. >> >> In other words, computations and manipulations with additions, multiplies >> and other logical operations (say of 32 bits) that compile nicely to for >> instance the computation of y=sin(t) in such a form that the Silicon >> Compiler can have a go at it, and produce a nice relative low-latency FPGA >> block to connect up with other blocks to do nice (and very low latency) DSP >> with. >> >> Regards, >> >> Theo V. >> _______________________________________________ >> dupswapdrop: music-dsp mailing list >> music-dsp@music.columbia.edu >> https://lists.columbia.edu/mailman/listinfo/music-dsp >> >> > > _______________________________________________ > dupswapdrop: music-dsp mailing list > music-dsp@music.columbia.edu > https://lists.columbia.edu/mailman/listinfo/music-dsp > -- Bjorn Roche @shimmeoapp
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