Thanks for your reply.  I appreciate the explanation.  However, I was hoping to 
find more information on the actual hardware implementation.  My CPU board is a 
plain Z80 CPU with 16 address lines to the bus.  There is no specific hardware 
for bank switching.  My memory board, currently being used as a 64K board (but 
with capability for more), has all 24 address lines with logic for placing the 
memory anywhere in the 24 bit address space, but no hardware for bank 
switching.  I am interested in building the bank-switching logic, but I cannot 
find details on how it’s done (or how others have done it.)  I would even be 
happy with a highly technical explanation of how bank switching works, over and 
above the 48/16 (or 32/32) structure described below.

 

Many thanks to anyone with further insight, details or examples.

 

Bob Bell

 

 

From: [email protected] [mailto:[email protected]] On 
Behalf Of Max Scane
Sent: Wednesday, December 31, 2014 4:13 PM
To: [email protected]
Subject: Re: [N8VEM-S100:5925] Bank Select Logic

 

Hi Bob,

 

A banked CP/M 3 implementation requires 2 memory regions:

 

1. Common.  This region is in high memory and extends to the top of logical 
(64KB) address space.  Depending on how much memory CP/M 3 needs for common 
data and drivers this would typically be 16KB or more.

 

2. Banked.  This region starts from location 0 and extends to the base of the 
common area and gets switched between several banks (typically two, TPA bank 
and the system bank) depending on the implementation.  The size depends on the 
size of the common bank.

 

Typical banking schemes are 48 KB banked with 16 KB common or  32/32 KB.

 

CP/M doesn't prescribe how the hardware implements banking beyond separating 
logical memory into the two regions and being able to swap out the banked area 
without impacting the common area.

 

MP/M takes this scheme a bit further and uses multiple memory banks to 
implement a multi-tasking and multi user system. 

 

The actual implementation is done in hardware either by the memory boards 
themselves (using a bank register and logic to implement the common area) or 
through the use of flat addressing  and a memory management unit on the CPU 
board.

 

The Z180 has an inbuilt MMU and is my favorite for this reason.

 

You will need to take a look at your CPU and memory boards to see what logic is 
available.  Some memory boards (such as the Expanroram) used a PROM to 
implement banking others used discreet logic.

 

I hope this helps.

 

Cheers

 

Max

 

On Wed, Dec 31, 2014 at 3:36 AM, Bob Bell <[email protected]> wrote:

Good Evening, most knowledgeable list.

I am in the process of building a second S-100 computer.  (My first one is now 
nearly 35 years old.)  I am hoping to use CPM3 on this new system in banked 
mode.  I have several 8-bit 64K S-100 memory boards I want to use, but while 
they all can be configured for 24-bit addressing, my CPU is a Z-80 that won't 
address anything higher than 64K.  I know CPM3 can be configured for using 
bank-select logic that takes an I/O port and latches that to the upper 8 
address lines, but I cannot find any solid information about how that is done 
or any particular standards that have been used.  Neither can I find any 
hardware that actually implements this bank-select function.  If anyone has 
familiarity with this hardware, the theory behind the function, or can point me 
in the right direction, I would be very thankful.

Bob Bell

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