Two things Bob, if you have the Intersystems Z80-II board you can modify it to do 16k bank select and use it with CPM3 see here:-
http://s100computers.com/Hardware%20Folder/Intersystems/Series%20II%20Z80%20CPU/Intersystems%20Z80-II.htm It’s a hack, but actually works fine. Second, I have not really sat down and tough the circuit you suggest out, but since you are on the “other side” of the Z80’s board bus drivers you need to be sure you are not going to blow yourself out of the water as you switch the RAM address lines for CPM bank selects. The code doing the switch process always has to be valid/available. Perhaps get it there via the stack or some fixed ROM routine. John From: [email protected] [mailto:[email protected]] On Behalf Of Bob Bell Sent: Thursday, January 1, 2015 8:27 AM To: [email protected] Subject: Re: [N8VEM-S100:5940] Bank Select Logic Thanks for the references - these are exactly what I was looking for and they are very helpful to see how others have done it. However, as I mentioned earlier, I have neither Z180 nor Z80 with on-board MMU as the CPU board you reference has. And the chances of buying/building such a board are not very high right now since I already have three Z80 CPU boards (two CCS 2810s and an Ithaca Intersystems Z80 board). So, since my memory boards are a full 64K, and they support extended addressing to 24 bits, I think it is possible to build a memory management unit that will utilize the port control like on John's CPU to latch various bits in the extended address range out to the bus. For example, if I, say, output a 00 to the MMU control port, it would decode that and set A16 to A23 to 00000000. One memory board would be set to be in the address range of hex 00 xx xx and would respond as bank 0. Then if I output, say, a 01 to the MMU, it would decode and latch A16 to A23 as 00000001. This is no longer in the first board's range, but a second memory board would be there. I think this implements the two-bank minimum for banked CPM3. The next question I have is this: are the 16K upper common sections in the two memory banks actually the same physical region of memory and the bank-switching logic has no effect on them (my suspicion pending confirmation), or can they be physically separate regions of memory as long as the exact same contents are written into both? I think I am beginning to see how this could work. Maybe the hardware implementation could even be done in a single GAL. Bob Bell On Wed, Dec 31, 2014 at 5:46 PM, Max Scane <[email protected]> wrote: The problem you are going to face is that the bank select logic or MMU needs to be inserted between the the Z80's address bus which becomes the logical address and the memory which is the physical address bus. The logic needs to manipulate the physical address lines depending on the bank boundaries etc. It is not just a matter of switching the high order address lines (A23 - A17) as that would give you 64 KB banks. For an example of a CPU board implementation, have a look at the N8VEM SBC http://n8vem-sbc.pbworks.com/w/file/28766758/sbcv2%20SBC-schematic.pdf The Memory Page Configuration Latches can implement a 48/16 or a 32/32 banking scheme. Also take a look at John's Z80 CPU board: http://www.s100computers.com/My%20System%20Pages/Z80%20Board/Z80%20CPU%20Board.htm There is a good write up of the banking scheme for that board. Cheers! Max On Wed, Dec 31, 2014 at 9:55 PM, Bob Bell <[email protected]> wrote: Thanks for your reply. I appreciate the explanation. However, I was hoping to find more information on the actual hardware implementation. My CPU board is a plain Z80 CPU with 16 address lines to the bus. There is no specific hardware for bank switching. My memory board, currently being used as a 64K board (but with capability for more), has all 24 address lines with logic for placing the memory anywhere in the 24 bit address space, but no hardware for bank switching. I am interested in building the bank-switching logic, but I cannot find details on how it’s done (or how others have done it.) I would even be happy with a highly technical explanation of how bank switching works, over and above the 48/16 (or 32/32) structure described below. Many thanks to anyone with further insight, details or examples. Bob Bell From: [email protected] [mailto:[email protected]] On Behalf Of Max Scane Sent: Wednesday, December 31, 2014 4:13 PM To: [email protected] Subject: Re: [N8VEM-S100:5925] Bank Select Logic Hi Bob, A banked CP/M 3 implementation requires 2 memory regions: 1. Common. This region is in high memory and extends to the top of logical (64KB) address space. Depending on how much memory CP/M 3 needs for common data and drivers this would typically be 16KB or more. 2. Banked. This region starts from location 0 and extends to the base of the common area and gets switched between several banks (typically two, TPA bank and the system bank) depending on the implementation. The size depends on the size of the common bank. Typical banking schemes are 48 KB banked with 16 KB common or 32/32 KB. CP/M doesn't prescribe how the hardware implements banking beyond separating logical memory into the two regions and being able to swap out the banked area without impacting the common area. MP/M takes this scheme a bit further and uses multiple memory banks to implement a multi-tasking and multi user system. The actual implementation is done in hardware either by the memory boards themselves (using a bank register and logic to implement the common area) or through the use of flat addressing and a memory management unit on the CPU board. The Z180 has an inbuilt MMU and is my favorite for this reason. You will need to take a look at your CPU and memory boards to see what logic is available. Some memory boards (such as the Expanroram) used a PROM to implement banking others used discreet logic. I hope this helps. Cheers Max On Wed, Dec 31, 2014 at 3:36 AM, Bob Bell <[email protected]> wrote: Good Evening, most knowledgeable list. I am in the process of building a second S-100 computer. (My first one is now nearly 35 years old.) I am hoping to use CPM3 on this new system in banked mode. I have several 8-bit 64K S-100 memory boards I want to use, but while they all can be configured for 24-bit addressing, my CPU is a Z-80 that won't address anything higher than 64K. I know CPM3 can be configured for using bank-select logic that takes an I/O port and latches that to the upper 8 address lines, but I cannot find any solid information about how that is done or any particular standards that have been used. Neither can I find any hardware that actually implements this bank-select function. If anyone has familiarity with this hardware, the theory behind the function, or can point me in the right direction, I would be very thankful. Bob Bell -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
