Hi John My comment is I am not sure that the 8255 is not the root of the problems at higher frequencies. Having to have the data valid for a min of 30 nsec after pWR* is de-asserted is going to be a problem. The GAL will help some but I think you would be served better by latching the data on the board. This is the only board so far that I have not been able to get to work with the 68k board. I will certainly take a couple of boards and see if it works better but if you are going to do a tweak on the board at least latch the data on write to 8255 if you insist on keeping it 8255 based.
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