You probably have a lot of space in the GALs for logic?

On Wednesday, February 11, 2015 at 8:18:00 PM UTC-6, monahanz wrote:
>
> So you’re suggesting latching the RD*/Data signals as well then Roger 
> using a 74LS373 and an inverted RD* (RD) as I did for the writes.  This 
> unfortunately will require another IC chip (I have run out of inverter 
> gates) but not a problem, plenty of room on this board.
>
>  
>
> Could everybody take a look at this schematic and let me know what you 
> thing.  (Remember LS373’s accept the data when clock is high, latch it when 
> clock returns low.  The OE*’s will be low/on for as long as the CPU will 
> allow (sINP or sOUT high).
>
>  
>
> John
>
>  
>
> *From:* [email protected] <javascript:> [mailto:
> [email protected] <javascript:>] 
> *Sent:* Wednesday, February 11, 2015 5:02 PM
> *To:* [email protected] <javascript:>
> *Subject:* Re: [N8VEM-S100:6296] Re: An updated (V3) version of our Dual 
> IDE/CF card S100 bus board
>
>  
>
>  
>
> >> One confusing thing is in what respect are we talking about read and 
> write. In terms of the S100 bus/CPU or 
> >>the 8255.    Let’s talk in terms of the CPU.
>
> >> Dave since you feel the problem is just with the CPU WR* signal  
> (particularly the 68K), then I will go back to 
> >>using the 74LS244 for the CPU read (S100 bus DI lines).
>
> When I designed my 68K SBC, I had a great deal of difficulty with the 68K 
> R/W* signal (particularly with reads, as I remember it).  I was able to get 
> a CF to work well with the Z80 (two SBC's) directly (no 8255), but the CF 
> seems to like a clean write or read pulse, and the 68K R/W* just didn't 
> seem to do it.  I had to go with an 8255 to get the CF to work with a 68K.  
> And it works quite well that way.  Maybe that's what you need to focus on 
> with the 68K CPU card (clean up R/W*)???
>
> Roger
>
>  
>
>  
>
>  
>
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