On Thu, 17 Oct 2019 at 15:15, <[email protected]> wrote: > But as you can see A) and B) can easily be tested with a single DUT (or some > small topology around it) using actual HW plugged in a loop with IXIA/Spirent > testers.
Snake topology does conserve IXIA/Spirent ports but will not allow you to test everything. I see no practical way of just having bunch of IXIA/Spirent ports to verify behaviour under various types of congestion. Unfortunately the 'bunch' is getting rather large, since even the smallest atom of a modern networking chip may contain dozens of 100GE ports. -- ++ytti
